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1. 发明申请

US20070253516A1 Jitter correction method and circuit 有权
标题翻译：抖动校正方法和电路
公开(公告)号：US20070253516A1
公开(公告)日：2007-11-01
申请号：US11520609
申请日：2006-09-14
申请人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
发明人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L1/205
摘要： In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.
摘要翻译：在抖动校正方法和电路中，通过将参考数据的1位时钟之后的数据的结束位和参考数据后的数据1个时钟的头位相加，结合数据组合数据。顺序地参考组合数据的每一位。当检测到参考位和与参考位直接相邻的位之间的变化时，并且当参考数量达到过采样的乘数并且未检测到包括参考位的至少三个相邻位之间的变化时，改变位置生成关于直接相邻位的显示数据作为参考数据的改变位，并且引用的数量被初始化。当未检测到变化，引用次数未达到乘数时，引用次数增加。从参考数据和改变位置显示数据中提取所有改变位，并且对应于乘数执行数据再现。

2. 发明授权

US08000429B2 Jitter correction method and circuit 有权
标题翻译：抖动校正方法和电路
公开(公告)号：US08000429B2
公开(公告)日：2011-08-16
申请号：US11520609
申请日：2006-09-14
申请人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
发明人： Hideo Abe , Yuji Obana , Hideaki Mochizuki
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04L1/205
摘要： In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.
摘要翻译：在抖动校正方法和电路中，通过将参考数据的1位时钟之后的数据的结束位和参考数据后的数据1个时钟的头位相加，结合数据组合数据。顺序地参考组合数据的每一位。当检测到参考位和与参考位直接相邻的位之间的变化时，并且当参考数量达到过采样的乘数并且未检测到包括参考位的至少三个相邻位之间的变化时，改变位置生成关于直接相邻位的显示数据作为参考数据的改变位，并且引用的数量被初始化。当未检测到变化，引用次数未达到乘数时，引用次数增加。从参考数据和改变位置显示数据中提取所有改变位，并且对应于乘数执行数据再现。

3. 发明授权

US07397882B2 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion 有权
标题翻译：数字锁相电路能够处理以突发方式提供的输入时钟信号
公开(公告)号：US07397882B2
公开(公告)日：2008-07-08
申请号：US10671593
申请日：2003-09-29
申请人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
发明人： Ichiro Yokokura , Yuji Obana , Hideaki Mochizuki
IPC分类号： H03D3/24
CPC分类号： H03L7/0993 , H03L7/107 , H04J3/076
摘要： A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.
摘要翻译：数字锁相电路提供输出时钟信号，其输出时钟信号的相位与期望的相位吸收特性水平下的输入时钟信号的相位同步，即使以突发方式提供输入时钟信号。相位比较部分将输出时钟信号的相位与输入时钟信号的相位进行比较。相位比较结果检测部分输出用于根据相位比较信号控制除法运算的INC / DEC请求信号。执行率计算部分根据INC / DEC请求信号计算输入时钟信号和输出时钟信号之间的相位差，并输出与相位差对应的执行速率。时钟产生部分根据INC / DEC请求信号控制主时钟信号的除法运算，并根据执行速率改变输出时钟信号的相位吸收速度。

4. 发明申请

US20100294306A1 METHOD AND SOLUTION FOR CLEANING SEMICONDUCTOR DEVICE SUBSTRATE 审中-公开
标题翻译：清洁半导体器件衬底的方法和解决方案
公开(公告)号：US20100294306A1
公开(公告)日：2010-11-25
申请号：US12746025
申请日：2008-12-03
申请人： Hideaki Mochizuki , Makoto Ishikawa , Noriyuki Saito
发明人： Hideaki Mochizuki , Makoto Ishikawa , Noriyuki Saito
IPC分类号： B08B3/12 , C11D3/43
CPC分类号： C11D3/044 , C11D1/72 , C11D3/2068 , C11D3/3947 , C11D7/06 , C11D7/263 , C11D11/0047 , H01L21/02052 , H01L21/02057
摘要： Provided is a method for cleaning a semiconductor device substrate, which is excellent in removability and re-adhesion-preventing properties of contaminations of fine particles or organic matter, metal contamination and combined contamination of organic matter and metal, which are adhered to a substrate surface, and which can highly clean the substrate surface without corroding it even when an intense ultrasonic wave is not applied.It is a method for cleaning a semiconductor device substrate, the method comprising cleaning the semiconductor device substrate while applying an ultrasonic wave having an intensity of 0.2 W or more and 1.5 W or less per cm2 of substrate to be irradiated with the ultrasonic wave by using a cleaning solution comprising the following components (A) to (D): (A) hydrogen peroxide, (B) an alkali, (C) water, and (D) a compound represented by the following general formula (1): R1—O—(—R2—O—)n—H(1) wherein R1 represents an alkyl group having 1 to 4 carbon atoms, R2 represents an alkylene group having 2 to 3 carbon atoms, and n represents an integer of 1 to 3.
摘要翻译：本发明提供一种清洁半导体器件基板的方法，该半导体器件基板具有优异的附着在基板表面上的细小颗粒或有机物污染物的可除去性和再粘合防止性，金属污染和有机物和金属的组合污染即使在不施加强烈的超声波的情况下，也可以高度清洁基板表面而不使其腐蚀。本发明是一种清洗半导体器件基板的方法，其特征在于，在施加超声波的情况下，通过使用0.2W以上且1.5W以下的超声波对每1cm 2的被照射超声波的基板进行清洗，包含以下组分（A）至（D）的清洁溶液：（A）过氧化氢，（B）碱，（C）水和（D）由以下通式（1）表示的化合物：R1- O - （ - R2-O-）n-H（1）其中R1表示碳原子数1〜4的烷基，R2表示碳原子数2〜3的亚烷基，n表示1〜3的整数。

5. 发明授权

US5723256A Color image forming process through transfer of image portion to receiving material, via cushion layer 失效
标题翻译：通过缓冲层将图像部分转印到接收材料上的彩色图像形成过程
公开(公告)号：US5723256A
公开(公告)日：1998-03-03
申请号：US665005
申请日：1996-05-15
申请人： Tetsuya Taniguchi , Kiyoshi Goto , Takeo Akiyama , Miyuki Hosoi , Tetsuya Masuda , Hideaki Mochizuki
发明人： Tetsuya Taniguchi , Kiyoshi Goto , Takeo Akiyama , Miyuki Hosoi , Tetsuya Masuda , Hideaki Mochizuki
IPC分类号： G03F3/10 , G03F7/09 , G03F7/40
CPC分类号： G03F7/09 , G03F3/10
摘要： Disclosed is a color image-formable material for forming and transferring a color image. The color image-formable material has a support, a cushion layer provided on the support and color light-sensitive layer containing a light-sensitive composition and a coloring agent provided on the cushion layer. It gives a transferred image by forming a color image portion by imagewise exposure and developing treatment and then transferring the color image portion alone to an image-receiving material. The cushion layer has a hardness of 40 to 85 and a thickness of 15 .mu.m to 100 .mu.m. A process for preparation of the color image-formable material is also disclosed.
摘要翻译：公开了一种用于形成和转印彩色图像的彩色图像形成材料。彩色成像材料具有支撑体，设置在支撑体上的缓冲层和含有感光组合物和设置在缓冲层上的着色剂的彩色感光层。通过图像曝光和显影处理形成彩色图像部分，然后将彩色图像部分单独转印到图像接收材料上，从而给出转印图像。缓冲层的硬度为40〜85，厚度为15μm〜100μm。还公开了制备彩色成像材料的方法。

6. 发明授权

US5517493A Line setting and phase adjusting apparatus for synchronous multiplex communications 失效
标题翻译：用于同步多路复用通信的线路设置和相位调整装置
公开(公告)号：US5517493A
公开(公告)日：1996-05-14
申请号：US215314
申请日：1994-03-21
申请人： Kimio Uekama , Hideaki Mochizuki
发明人： Kimio Uekama , Hideaki Mochizuki
IPC分类号： H04J3/00 , H04J3/06 , H04J3/16 , H04Q11/04 , H04L12/52
CPC分类号： H04J3/0623
摘要： The setting and phase adjusting apparatus for synchronous multiplex communications is provided which adjusts phase differences of main signals caused between a plurality of synchronous multiplexing sections and a line setting section during line setting, in which to reduce the scale of circuitry of the line setting section in a transmission device for carrying out multiplexing and line setting on large-capacity signals, a plurality of pointer modifiers are arranged on a shelf on which the line setting section is arranged. The pointer modifiers connect the line setting section to the respective synchronous multiplexing sections. The pointer modifiers are supplied with multiplexed signals of respective signal series whose data head positions are shifted from one another. The head positions of these signals are synchronized with a timing signal from a timing generator by the pointer modifiers. Line switching is then effected by time switches and a space switch.
摘要翻译：提供了用于同步多路复用通信的设置和相位调整装置，其调节在线路设置期间在多个同步多路复用部分和线路设置部分之间引起的主信号的相位差，其中减少线路设置部分的电路规模用于在大容量信号上执行多路复用和线路设置的传输设备，多个指示器改进器被布置在布置有线路设置部分的架子上。指针修改器将线路设置部分连接到各个同步复用部分。指针修改器被提供有数据头位置彼此偏移的各个信号序列的多路复用信号。这些信号的头部位置与来自定时发生器的定时信号通过指针调节器同步。然后线路切换由时间开关和空间开关实现。

7. 发明授权

US07418036B2 Method and circuit for timing pulse generation 失效
标题翻译：定时脉冲发生的方法和电路
公开(公告)号：US07418036B2
公开(公告)日：2008-08-26
申请号：US10790879
申请日：2004-03-03
申请人： Hideaki Mochizuki
发明人： Hideaki Mochizuki
IPC分类号： H03K7/04 , H03K7/06 , H03K9/04 , H03K9/06
CPC分类号： G06F1/10 , H03K5/1252
摘要： In a method and a circuit for timing pulse generation, a frame pulse of a corresponding system is masked when an alarm signal of either a working system or a protection system is received, a monitoring window which indicates an absorbable range of delay time difference between the frame pulses is generated upon an arrival of the frame pulse of the system selected by a switching signal, when the alarm signal of a system not selected is generated upon selection of the switching signal. Alternatively, a request signal for regenerating the monitoring window which indicates an absorbable range of delay time difference between the frame pulses is provided upon an arrival of the frame pulse of the system selected by the switching signal, when a slip signal is generated upon selection of the switching signal. The monitoring window is generated around the frame pulse selected by the switching signal when the monitoring window generation request signal is received, a read timing pulse common to memories of both systems is generated at a predetermined timing position, and the monitoring window is regenerated when the selected frame pulse deviates from the monitoring window. Alternatively, a correction signal including a number and a direction of bits when a reference timing pulse not selected deviates from the monitoring window is generated to be transmitted, the correction signal is extracted from a main signal received, and a position of the reference timing pulse of the protection system is corrected based on the correction signal, when the protection system is presently selected.
摘要翻译：在用于定时脉冲产生的方法和电路中，当接收到工作系统或保护系统的报警信号时，相应系统的帧脉冲被屏蔽，监视窗口指示在所述工作系统或保护系统之间的延迟时间差的可吸收范围当选择切换信号时，当未选择的系统的报警信号产生时，通过切换信号选择的系统的帧脉冲的到达产生帧脉冲。或者，当选择了滑移信号时，在通过切换信号选择的系统的帧脉冲的到达时，提供用于再生指示帧脉冲之间的可延迟时间差的可吸收范围的监视窗口的请求信号开关信号。当接收到监视窗口生成请求信号时，围绕由切换信号选择的帧脉冲产生监视窗口，在预定的定时位置产生对两个系统的存储器共同的读定时脉冲，并且当监视窗口在选定的帧脉冲偏离监视窗口。或者，产生包括当未选择的基准定时脉冲偏离监视窗口时的位数和位置方向的校正信号被发送，从接收的主信号中提取校正信号，并且将参考定时脉冲当保护系统当前被选择时，基于校正信号来校正保护系统。

8. 发明授权

US07304998B2 Fixed length data processing apparatus 失效
标题翻译：固定长度数据处理装置
公开(公告)号：US07304998B2
公开(公告)日：2007-12-04
申请号：US10602348
申请日：2003-06-23
申请人： Kazuhisa Kada , Hiroshi Murakawa , Shigehisa Sakahara , Hidenori Kiuchi , Hideaki Mochizuki , Ritsuko Okura
发明人： Kazuhisa Kada , Hiroshi Murakawa , Shigehisa Sakahara , Hidenori Kiuchi , Hideaki Mochizuki , Ritsuko Okura
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04J3/14 , H04J2203/0042 , H04J2203/006 , H04J2203/008 , H04L2012/5605 , H04L2012/5612
摘要： A fixed length data processing apparatus has a registration holding unit holding registration information necessary to identify fixed length data that is an object of a processing commonly to transmission routes, and a data processing unit identifying whether received fixed length data is fixed length data that is an object of the processing or not on the basis of at least the registration information in the registration information holding unit to perform a data processing for fault management in the asynchronous communication on the basis of the fixed length data when identifying that the fixed length data is fixed length data that is an object of a processing correspondingly to the transmission route, thereby holding a large volume of information efficiently for identifying fixed length data to process fixed length data with a simple structure.
摘要翻译：固定长度数据处理装置具有登记保持单元，其保存用于识别作为传输路由共同处理的对象的固定长度数据所必需的登记信息，以及数据处理单元，其识别接收到的固定长度数据是否是固定长度数据，至少基于注册信息保持单元中的注册信息来执行处理的对象，以便在识别出固定长度数据是固定的时候基于固定长度数据执行异步通信中的故障管理的数据处理作为对应于传输路由的处理对象的长度数据，从而有效地保存大量的信息以识别固定长度的数据，以简单的结构处理固定长度的数据。

9. 发明授权

US07042836B2 Transmitting apparatus 失效
标题翻译：传送装置
公开(公告)号：US07042836B2
公开(公告)日：2006-05-09
申请号：US09753903
申请日：2001-01-03
申请人： Ritsuko Isonuma , Hideaki Mochizuki
发明人： Ritsuko Isonuma , Hideaki Mochizuki
IPC分类号： H04L1/00
CPC分类号： H04J3/085
摘要： A transmitting apparatus for cross connecting and transmitting main signals which enter via ring-configured transmission lines to which working and protection channels have been assigned in first and second directions, and rescuing a main signal by looping back the main signal in the opposite direction using the protection channel when a transmission line fails. Storing non-rescue information which indicates whether each channel that is the object of rescue by loop-back is a non-rescue channel. Determining whether a failure for which rescue is impossible has occurred in each channel, which is the object of rescue, other than a non-rescue channel. On the basis of main-signal cross-connect information, interchanging a result of discrimination of each channel and inserting the interchanged result of discrimination in the main signal of the corresponding channel after cross connect.
摘要翻译：一种用于交叉连接和传送主信号的发送装置，所述主信号通过在第一和第二方向被分配了工作和保护信道的环形传输线路进入，并且通过使用所述主信号通过相反方向回放主信号来拯救主信号传输线路故障时的保护通道。存储表示是否通过回送作为救援对象的每个频道是非救援信道的非救援信息。确定除救援通道之外，作为救援对象的每个通道是否发生了不可救援的故障。在主信号交叉连接信息的基础上，交换每个通道的辨别结果，并将互换后的辨别结果插入交叉连接后相应通道的主信号。

10. 发明授权

US06594237B1 Fixed length data processing apparatus 失效
标题翻译：固定长度数据处理装置
公开(公告)号：US06594237B1
公开(公告)日：2003-07-15
申请号：US09280881
申请日：1999-03-29
申请人： Hidenori Kiuchi , Hiroshi Murakawa , Shigehisa Sakahara , Kazuhisa Kada , Hideaki Mochizuki , Ritsuko Okura
发明人： Hidenori Kiuchi , Hiroshi Murakawa , Shigehisa Sakahara , Kazuhisa Kada , Hideaki Mochizuki , Ritsuko Okura
IPC分类号： G01R3108
CPC分类号： H04L12/5601 , H04L2012/5612 , H04L2012/5625 , H04L2012/5627 , H04L2012/5642
摘要： A fixed length data processing apparatus has a data processing unit receiving at least fixed length data to perform a desired data processing on the fixed length data, and an operation state monitoring process unit performing a monitoring process to monitor an operation state of an asynchronous communication on the basis of the fixed length data received by said data processing unit, thereby detecting loss or misinsertion of fixed length data such as an ATM cell or the like and monitoring a flow state in a transmission system having a high transmission rate.
摘要翻译：固定长度数据处理装置具有：数据处理单元，至少接收固定长度数据，对固定长度数据执行期望的数据处理;以及操作状态监视处理单元，执行用于监视异步通信的操作状态的监视处理由所述数据处理单元接收的固定长度数据的基础，从而检测诸如ATM信元等的固定长度数据的丢失或误插，并监视具有高传输速率的传输系统中的流量状态。

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