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1. 发明申请

US20070273028A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY 有权
标题翻译：包含由导体层连接的不同级别互连层的半导体集成电路器件，包括用于冗余的导体层
公开(公告)号：US20070273028A1
公开(公告)日：2007-11-29
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

2. 发明申请

US20100095443A1 TOILET SEAT APPARATUS 有权
标题翻译：卫生间座椅装置
公开(公告)号：US20100095443A1
公开(公告)日：2010-04-22
申请号：US12530678
申请日：2008-03-11
申请人： Makoto Nishimura , Shigeru Shirai , Hideki Ohno , Yoshiharu Shimada , Tomoko Ishida , Yuji Yamamoto , Shinji Fujii , Yoshiko Kurimoto , Kazuya Kondoh , Masahiro Inoue , Toru Ueno
发明人： Makoto Nishimura , Shigeru Shirai , Hideki Ohno , Yoshiharu Shimada , Tomoko Ishida , Yuji Yamamoto , Shinji Fujii , Yoshiko Kurimoto , Kazuya Kondoh , Masahiro Inoue , Toru Ueno
IPC分类号： A47K13/00
CPC分类号： A47K13/24 , A47K13/305 , H05B3/26 , H05B3/267 , H05B3/56 , H05B2203/014 , H05B2203/017 , H05B2203/029
摘要： A linear heater is formed of an enamel wire composed of a heating wire and an enamel layer. The heating wire is made of a copper alloy containing silver, for example. The enamel layer is made of polyester imide (PEI), polyimide (PI) or polyamide imide (PAI), for example. The enamel layer is coated with an insulating coating layer. The insulating coating layer is made of fluororesin such as perfluoroalkoxy mixture (PFA), polyimide (PI), or polyamide imide (PAI). The linear heater is bonded to the lower surface of an upper toilet seat casing such that it is sandwiched between a metal foil and a metal foil made of aluminum, for example.
摘要翻译：线状加热器由由加热线和搪瓷层组成的搪瓷线形成。例如，加热线由含有银的铜合金构成。搪瓷层例如由聚酰亚胺（PEI），聚酰亚胺（PI）或聚酰胺酰亚胺（PAI）制成。搪瓷层涂有绝缘涂层。绝缘涂层由全氟烷氧基混合物（PFA），聚酰亚胺（PI）或聚酰胺酰亚胺（PAI）等氟树脂制成。线状加热器例如被接合到上座便器壳体的下表面，使得其被夹在金属箔和铝制金属箔之间。

3. 发明申请

US20090123844A1 Lithium Primary Battery and Manufacturing Method Therefor 有权
标题翻译：锂一次电池及其制造方法
公开(公告)号：US20090123844A1
公开(公告)日：2009-05-14
申请号：US11720151
申请日：2005-10-07
申请人： Kenichi Morigaki , Susumu Yamanaka , Tohru Hitomi , Shinji Fujii , Toshihiko Ikehata
发明人： Kenichi Morigaki , Susumu Yamanaka , Tohru Hitomi , Shinji Fujii , Toshihiko Ikehata
IPC分类号： H01M4/40 , H01M4/62 , H01M4/58 , H01M4/04
CPC分类号： H01M6/16 , H01M4/06 , H01M4/08 , H01M4/366 , H01M4/382 , H01M4/405 , H01M4/505 , H01M4/5835 , H01M4/62 , H01M4/625 , H01M6/164 , H01M6/166 , H01M2300/0028 , Y10T29/49108
摘要： A lithium primary battery including a positive electrode, a negative electrode, an organic electrolyte, and a separator interposed between the positive electrode and the negative electrode: the negative electrode including a negative electrode active material; the negative electrode active material being at least one selected from the group consisting of lithium metal and a lithium alloy; at least a surface layer portion of the negative electrode including a composite of amorphous carbon material and the negative electrode active material; and the surface layer portion facing the positive electrode with the separator interposed therebetween.
摘要翻译：一种锂一次电池，包括正极，负极，有机电解质和置于正极和负极之间的隔膜：负极包括负极活性材料; 所述负极活性物质为选自锂金属和锂合金中的至少一种; 负极的至少一个表层部分包括非晶碳材料和负极活性材料的复合物; 并且所述表面层部分面对所述正极，并且所述隔膜插入其间。

4. 发明申请

US20060009039A1 Etching method, etching apparatus, and method for manufacturing semiconductor device 审中-公开
标题翻译：蚀刻方法，蚀刻装置以及半导体装置的制造方法
公开(公告)号：US20060009039A1
公开(公告)日：2006-01-12
申请号：US11203110
申请日：2005-08-15
申请人： Shinji Fujii
发明人： Shinji Fujii
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/31111
摘要： In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.
摘要翻译：为了通过湿蚀刻可靠地除去含有金属和硅的化合物，例如含有铪金属的硅酸盐（101a），硅酸盐（101a）被氧化，然后氧化的硅酸盐（101a）被湿润，蚀刻。

5. 发明授权

US4994687A Retriggerable multivibrator 失效
标题翻译：可再触发多谐振荡器
公开(公告)号：US4994687A
公开(公告)日：1991-02-19
申请号：US277112
申请日：1988-11-29
申请人： Shinji Fujii , Ikuo Tsuchiya , Kazuhiko Kasai
发明人： Shinji Fujii , Ikuo Tsuchiya , Kazuhiko Kasai
IPC分类号： H03K3/02 , H03K3/033
CPC分类号： H03K3/033
摘要： A retriggerable multivibrator is disclosed which comprises a first delay circuit connected for delaying an input signal a predetermined time, a second delay circuit connected to receive an output of the first delay circuit and having a enable or disable function, a flip-flop circuit connected to be set or reset in accordance with an input signal and output signal from the second delay circuit, and a control circuit for detecting a subsequent input signal within a predetermined delay time to enable or disable the second delay circuit.

6. 发明授权

US08030773B2 Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy 有权
标题翻译：半导体集成电路器件包括由导体层连接的不同级别的互连层，包括用于冗余的导体层
公开(公告)号：US08030773B2
公开(公告)日：2011-10-04
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

7. 发明申请

US20100009268A1 LITHIUM PRIMARY BATTERY 审中-公开
标题翻译：锂电池
公开(公告)号：US20100009268A1
公开(公告)日：2010-01-14
申请号：US12444542
申请日：2006-10-18
申请人： Tohru Hitomi , Susumu Yamanaka , Shinji Fujii , Kenichi Takata , Kenichi Morigaki
发明人： Tohru Hitomi , Susumu Yamanaka , Shinji Fujii , Kenichi Takata , Kenichi Morigaki
IPC分类号： H01M6/14 , H01M4/58 , H01M4/48
CPC分类号： H01M4/587 , H01M4/06 , H01M4/364 , H01M4/405 , H01M4/485 , H01M4/505 , H01M4/525 , H01M4/5835 , H01M6/164 , H01M6/166
摘要： The present invention intends to provide a lithium primary battery excellent in large-current discharge characteristics in a low temperature environment without sacrificing the high-temperature storage characteristics. The present invention relates to a lithium primary battery including a positive electrode including a fluoride as a positive electrode active material, a negative electrode including metallic lithium or a lithium alloy as a negative electrode active material, a separator interposed between the positive electrode and the negative electrode, and an electrolyte. The positive electrode further includes a metal oxide being capable of absorbing and desorbing lithium ions, having a spinel structure, and having a discharge potential versus lithium lower than that of the fluoride.
摘要翻译：本发明旨在提供在低温环境下具有优异的大电流放电特性的锂一次电池，而不牺牲高温储存特性。本发明涉及一种锂一次电池，其包括正极，其包括作为正极活性物质的氟化物，包含金属锂或锂合金的负极作为负极活性物质，插入在正极和负极之间的隔膜电极和电解质。该正极还包括能够吸收和解吸锂离子的金属氧化物，其具有尖晶石结构，并且具有与锂的放电电位相对于低于氟化物的放电电位。

8. 发明申请

US20080073728A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080073728A1
公开(公告)日：2008-03-27
申请号：US11858173
申请日：2007-09-20
申请人： Shinji Fujii , Kouichirou Inoue , Naoto Higuchi , Taisei Suzuki
发明人： Shinji Fujii , Kouichirou Inoue , Naoto Higuchi , Taisei Suzuki
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0705
摘要： Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate, a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate, and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.
摘要翻译：公开了即使使用相移掩模来构图MISFET的栅电极的电流特性也能够防止其变化的半导体器件及其制造方法。根据本发明的一个方面，提供了一种半导体器件，包括：第一晶体管，包括设置在半导体衬底上的第一栅电极，以及设置在半导体衬底中的第一源极和第一漏极;第二晶体管，被布置为并且包括设置在所述半导体衬底上的与所述第一栅电极并联的第二栅电极，以及设置在所述半导体衬底中的第二源极和第二漏极，以及设置在所述第一晶体管和所述第一晶体管之间的第三栅电极，第二晶体管并且与第一和第二栅电极并联。

9. 发明授权

US5406135A Differential current source circuit in DAC of current driving type 失效
标题翻译：电流驱动型DAC中的差分电流源电路
公开(公告)号：US5406135A
公开(公告)日：1995-04-11
申请号：US156627
申请日：1993-11-24
申请人： Kazuhiko Kasai , Kenji Matsuo , Shinji Fujii , Yasukazu Noine
发明人： Kazuhiko Kasai , Kenji Matsuo , Shinji Fujii , Yasukazu Noine
IPC分类号： G05F3/24 , H03F3/45 , H03K17/041 , H03K17/693 , H03M1/74 , H03M3/02 , H03F3/16
CPC分类号： H03K17/04106 , H03K17/693
摘要： A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.
摘要翻译：差分电流源电路包括三个P沟道MOSFET和两个N沟道MOSFET。第一和第二P沟道MOSFET的每个源连接到电源，并且偏置电压施加到MOSFET的每个栅极。第一N沟道MOSFET的电流路径连接在第一P沟道MOSFET的漏极和地之间。第三P沟道MOSFET的电流路径连接在第二P沟道MOSFET的漏极和电流输出端子之间。第三P沟道MOSFET的栅极连接到第一P沟道MOSFET的漏极。第二N沟道MOSFET的电流路径的一端连接到第一P沟道和第一N沟道MOSFET的连接点，另一端连接到第二P沟道和第三N沟道MOSFET的连接点 P沟道MOSFET。数字信号被施加到第二N沟道MOSFET的栅极。

10. 发明授权

US5369318A Level translator capable of high speed operation 失效
标题翻译：能够高速运行的电平转换器
公开(公告)号：US5369318A
公开(公告)日：1994-11-29
申请号：US80109
申请日：1993-06-23
申请人： Tadahiro Kuroda , Shinji Fujii , Masahiro Kimura , Kazuhiko Kasai
发明人： Tadahiro Kuroda , Shinji Fujii , Masahiro Kimura , Kazuhiko Kasai
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/00384 , H03K19/017518
摘要： The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.
摘要翻译： ECL电路的输出端直接连接到CMOS输出电路的输入端。 CMOS输出电路具有将CMOS输出电路的阈值电压设置在ECL逻辑电平几乎中间的晶体管。第一参考电压产生电路具有与CMOS输出电路基本相同的布置，并将作为第一参考电压Vref1的CMOS逻辑电平之间的电位输出。第一参考电压Vref1变为可变的。第二参考电压产生电路具有与ECL电路基本相同的布置，并将作为第二参考电压Vref2的ECL逻辑电平之间的电位输出。比较器比较第一和第二参考电压Vref1和Vref2，并控制第一参考电压产生电路和CMOS输出电路，使得第一和第二参考电压Vref1和Vref2可以彼此相等。

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