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1. 发明申请

US20070273028A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY 有权
标题翻译：包含由导体层连接的不同级别互连层的半导体集成电路器件，包括用于冗余的导体层
公开(公告)号：US20070273028A1
公开(公告)日：2007-11-29
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

2. 发明授权

US08030773B2 Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy 有权
标题翻译：半导体集成电路器件包括由导体层连接的不同级别的互连层，包括用于冗余的导体层
公开(公告)号：US08030773B2
公开(公告)日：2011-10-04
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

3. 发明申请

US20060199325A1 Semiconductor integrated circuit device advantageous for microfabrication and manufacturing method for the same 审中-公开
标题翻译：有利于微加工的半导体集成电路器件及其制造方法
公开(公告)号：US20060199325A1
公开(公告)日：2006-09-07
申请号：US11365087
申请日：2006-02-28
申请人： Muneaki Maeno , Toshikazu Sei
发明人： Muneaki Maeno , Toshikazu Sei
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L27/11807
摘要： A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type which are provided in the well such that the first diffusion layers sandwich the gate electrode, the first diffusion layers functioning as sources/drains. The device further includes sub-regions which are arranged in a non-occupied area of the logic circuit structure region, each of the sub-regions including a conductive layer, which is provided on the well and has the same pattern shape as the gate electrode, and second diffusion layers of the first conductivity type, which have the same pattern shape as the first diffusion layers and are disposed spaced apart to sandwich the conductive layer, the second diffusion layers being electrically connected to the well.
摘要翻译：半导体集成电路器件包括单元，每个单元包括设置在阱上的栅电极和设置在阱中的第二导电类型的第一扩散层，使得第一扩散层夹着栅电极，第一扩散层用作源/排水管。该器件还包括布置在逻辑电路结构区域的非占用区域中的子区域，每个子区域包括导体层，该导电层设置在阱上并具有与栅电极相同的图案形状以及第一导电类型的第二扩散层，其具有与第一扩散层相同的图案形状并且间隔设置以夹持导电层，第二扩散层电连接到阱。

4. 发明授权

US06753611B1 Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program 有权
公开(公告)号：US06753611B1
公开(公告)日：2004-06-22
申请号：US09658452
申请日：2000-09-08
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

5. 发明授权

US08274319B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08274319B2
公开(公告)日：2012-09-25
申请号：US12723796
申请日：2010-03-15
申请人： Muneaki Maeno
发明人： Muneaki Maeno
IPC分类号： H03K3/289
CPC分类号： H03K3/356156 , H03K3/35625
摘要： A semiconductor device includes a flip-flop circuit formed in a CMOS semiconductor integrated circuit. The flip-flop circuit includes at least a first clock generating inverter that generates a first clock signal and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit, the latch unit including a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter.
摘要翻译：半导体器件包括形成在CMOS半导体集成电路中的触发电路。触发器电路至少包括产生第一时钟信号的第一时钟产生逆变器和产生通过反相第一时钟信号而获得的第二时钟信号的第二时钟产生逆变器，第一时钟产生逆变器和第二时钟发生逆变器被布置成夹着锁存单元，所述锁存单元包括在所述触发器电路中的主锁存单元和从锁存单元，所述触发器电路中的所述第一时钟发生反相器和第一其他电路被配置为共享源极区域，与第一时钟发生反相器相邻的第一其它电路，以及触发器电路中的第二时钟产生反相器和第二另外的电路，被配置为共享源极区域，第二另外的电路与第二时钟发生逆变器。

6. 发明申请

US20070267680A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20070267680A1
公开(公告)日：2007-11-22
申请号：US11749274
申请日：2007-05-16
申请人： Yukinori Uchino , Muneaki Maeno , Yoichi Takegawa , Hisato Oyamatsu
发明人： Yukinori Uchino , Muneaki Maeno , Yoichi Takegawa , Hisato Oyamatsu
IPC分类号： H01L29/788
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/092
摘要： A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors are provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.
摘要翻译：一种半导体集成电路器件包括包括多个N沟道晶体管和多个P沟道晶体管的CMOS电路。多个N沟道晶体管通过栅极隔离结构和浅沟槽隔离结构之一提供器件隔离。多个P沟道晶体管被栅极隔离结构和浅沟槽隔离结构中的另一个提供器件隔离。

7. 发明授权

US06888254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06888254B2
公开(公告)日：2005-05-03
申请号：US09966440
申请日：2001-09-27
申请人： Akira Yamaguchi , Muneaki Maeno
发明人： Akira Yamaguchi , Muneaki Maeno
IPC分类号： H01L21/82 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/10 , H01L23/04 , H01L23/053 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/73
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.
摘要翻译：第一和第二IP内核形成在一个芯片上。第一和第二IP核中的每个具有金属层。在第一IP核中，金属层的最上层是厚的，并且是形成有核心电源线的层。在第二IP核中，与第一IP核中的最上层相等的金属层变成中间层。在第二IP核中，在该中间层上形成薄的中间层。薄的中间层是其上形成信号线并且具有窄布线间距的层。在第二IP核中，在薄中间层上设置有形成有电源线的层。

8. 发明授权

US5978301A Gate array LSI 失效
标题翻译：门阵列LSI
公开(公告)号：US5978301A
公开(公告)日：1999-11-02
申请号：US922024
申请日：1997-09-02
申请人： Muneaki Maeno , Yukinori Uchino , Yutaka Tanaka
发明人： Muneaki Maeno , Yukinori Uchino , Yutaka Tanaka
IPC分类号： G11C11/405 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/118
CPC分类号： H01L27/11807 , H01L27/105
摘要： The present invention relates to the improvement in the degree of on-chip integration of memory cells utilizing a gate array layout. A plurality of three-transistor DRAM cells are disposed on a semiconductor chip implementing a regular cross-point array, each DRAM cell is made up of two nMOS transistors and one pMOS transistor formed in one basic cell. The semiconductor chip disposes therein nMOS memory-cell blocks and pMOS memory-cell blocks alternately, effectively utilizing the gate array layout.
摘要翻译：本发明涉及使用门阵列布局的存储单元的片上集成程度的改进。在实现规则交叉点阵列的半导体芯片上设置多个三晶体管DRAM单元，每个DRAM单元由两个nMOS晶体管和一个形成在一个基本单元中的一个pMOS晶体管组成。半导体芯片交替地配置有nMOS存储单元块和pMOS存储单元块，有效地利用了栅极阵列布局。

9. 发明授权

US07444614B2 Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal 有权
标题翻译：存储半导体设计程序的计算机可读记录介质，用于改善通孔接触和金属的集成和连接
公开(公告)号：US07444614B2
公开(公告)日：2008-10-28
申请号：US10968925
申请日：2004-10-21
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.
摘要翻译：半导体器件具有通孔接触，主线的端部连接到通孔接触，以及从主线的端部延伸成与主线成直线延伸超过通孔接触的延伸部，延伸部的宽度等于或窄于主导线的宽度。该延伸部通过光学接近效应防止主线的端部变圆，消除了通孔接触和主线的端部之间的接触缺陷或开放缺陷，并且不涉及导线围绕通孔的变宽 - 接触，使得其他通孔接触可以布置在所述通孔接触的附近，而不违反设计规则。

10. 发明申请

US20060012050A1 Semiconductor device, designing method thereof, and recording medium storing semicondcutor designing program 有权
标题翻译：半导体器件，其设计方法以及存储半衰落设计程序的记录介质
公开(公告)号：US20060012050A1
公开(公告)日：2006-01-19
申请号：US10968925
申请日：2004-10-21
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.
摘要翻译：半导体器件具有通孔接触，主线的端部连接到通孔接触，以及从主线的端部延伸成与主线成直线延伸超过通孔接触的延伸部，延伸部的宽度等于或窄于主导线的宽度。该延伸部通过光学接近效应防止主线的端部变圆，消除了通孔接触和主线的端部之间的接触缺陷或开放缺陷，并且不涉及导线围绕通孔的变宽 - 接触，使得其他通孔接触可以布置在所述通孔接触的附近，而不违反设计规则。

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