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1. 发明授权

US06310656B1 Television apparatus, display method of television apparatus and picture plane control apparatus, and method 失效
标题翻译：电视机，电视机的显示方法及画面控制装置及方法
公开(公告)号：US06310656B1
公开(公告)日：2001-10-30
申请号：US09353234
申请日：1999-07-14
申请人： Shinichiro Miyazaki , Yoshinobu Tsunetomi , Akira Shirahama
发明人： Shinichiro Miyazaki , Yoshinobu Tsunetomi , Akira Shirahama
IPC分类号： H04N545
CPC分类号： H04N5/45 , H04N7/0122 , H04N21/4263 , H04N21/4316
摘要： In a divider, a ratio of a magnification or a reduction of an image is set from a writing range and a reading range. In a horizontal interpolating circuit and a vertical interpolating circuit, an interpolation is performed on the basis of the magnification ratio. In the horizontal interpolating circuit and the vertical interpolating circuit, an interpolation is performed on the basis of the reduction ratio. In a field memory, a portion of the image of an arbitrary size at an arbitrary position is written on the basis of a control signal which is supplied from a write memory control circuit. The image is read out from the memory on the basis of a control signal which is supplied from a read memory control circuit.
摘要翻译：在分频器中，从写入范围和读取范围设定图像的倍率或缩小比。在水平内插电路和垂直内插电路中，基于放大率进行内插。在水平内插电路和垂直内插电路中，基于缩小比进行插值。在场存储器中，基于从写入存储器控制电路提供的控制信号来写入任意位置的任意大小的图像的一部分。基于从读存储器控制电路提供的控制信号，从存储器读出图像。

2. 发明授权

US06311328B1 Apparatus and method for enlarging/reducing a video picture size 失效
标题翻译：用于放大/缩小视频图像尺寸的装置和方法
公开(公告)号：US06311328B1
公开(公告)日：2001-10-30
申请号：US08867768
申请日：1997-06-03
申请人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ono , Nobou Ueki
发明人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ono , Nobou Ueki
IPC分类号： H04N1393
CPC分类号： G06T3/4007
摘要： A picture processing apparatus for picture-in-picture applications where the number of pixels n in the horizontal direction of an original picture, the number of pixels m in the vertical direction thereof, the number of pixels N in the horizontal direction of the converted picture, and the number of pixels M in the vertical direction thereof are supplied to a dividing device. Thus, ratios A=N/n and B=M/m are obtained. The inverse number 1/A of the value A is cumulated by circuits. An address generating circuit generates addresses at four points for calculating a density value a of a converted pixel corresponding to the integer part of a cumulated value &Sgr;(1/A). These addresses are supplied to memories. The pixel data at the four points that are read from the memories are supplied to respective multiplying devices. The decimal part of the value &Sgr;(1/A) is supplied as an interpolating coefficient p to a multiplying device. A coefficient (1−q) is supplied to a multiplying device. Likewise, in the vertical direction, coefficients q and (1−q) are supplied to respective multiplying devices. These multiplying devices and adding devices perform operations. Thus, the density value a of the converted pixel is obtained and supplied from a terminal.
摘要翻译：一种用于画中画应用的图像处理装置，其中原始图像的水平方向上的像素数n，垂直方向上的像素数m，转换图像的水平方向上的像素数N ，并且其垂直方向上的像素数M被提供给分割装置。因此，获得比A = N / n和B = M / m。值A的倒数1 / A由电路累积。地址发生电路在四点产生地址，用于计算与累积值SIGMA（1 / A）的整数部分对应的转换像素的浓度值a。这些地址被提供给存储器。从存储器读取的四个点处的像素数据被提供给各个乘法装置。值SIGMA（1 / A）的小数部分作为内插系数p提供给乘法装置。系数（1-q）被提供给乘法装置。类似地，在垂直方向上，系数q和（1-q）被提供给各个乘法装置。这些乘法装置和附加装置执行操作。因此，从终端获得并提供转换像素的密度值a。

3. 发明授权

US06822694B2 Signal processing apparatus 失效
标题翻译：信号处理装置
公开(公告)号：US06822694B2
公开(公告)日：2004-11-23
申请号：US09203923
申请日：1998-12-02
申请人： Shinichiro Miyazaki , Hiroyuki Kojima , Akira Shirahama , Hiroshi Sugaya
发明人： Shinichiro Miyazaki , Hiroyuki Kojima , Akira Shirahama , Hiroshi Sugaya
IPC分类号： H04N968
CPC分类号： H04N9/76
摘要： According to the signal processing apparatus of the present invention, in a text signal processing circuit, predetermined signal processes are executed to a luminance signal Y and color difference signals U and V in which a ratio of sampling clocks is equal to (4:4:4) and resultant signals are supplied to a mixing circuit. In a video signal processing circuit, predetermined signal processes are executed to the signals Y, U, and V in which a ratio of sampling clocks is equal to (4:1:1) or (4:2:2). The signal Y is supplied to the mixing circuit through a delay adjusting circuit and the high frequency components are removed from the signals U and V by a band limiting filter and, after that, the resultant signals are supplied to the mixing circuit. The signal mixed by the mixing circuit is supplied to a LPF through a D/A converter. In the LPF, the signal is demodulated by the band limiting filter according to (4:4:4).
摘要翻译：根据本发明的信号处理装置，在文本信号处理电路中，对亮度信号Y和采样时钟的比例等于（4:4:4）的色差信号U，V执行规定的信号处理， 4），并将合成信号提供给混合电路。在视频信号处理电路中，对采样时钟的比例等于（4:1:1）或（4:2:2）的信号Y，U和V执行预定的信号处理。信号Y通过延迟调整电路提供给混合电路，并通过频带限制滤波器从信号U和V中去除高频分量，然后将所得到的信号提供给混频电路。由混合电路混合的信号通过D / A转换器提供给LPF。在LPF中，信号由（4：4：4）的带限滤波器解调。

4. 发明授权

US07151572B2 Apparatus and method for processing predetermined program data 有权
标题翻译：用于处理预定程序数据的装置和方法
公开(公告)号：US07151572B2
公开(公告)日：2006-12-19
申请号：US09854287
申请日：2001-05-11
申请人： Akira Shirahama , Shinichiro Miyazaki , Seigo Hirakawa
发明人： Akira Shirahama , Shinichiro Miyazaki , Seigo Hirakawa
IPC分类号： H04N5/44 , H04N7/00 , H04N7/08 , H04N11/00
CPC分类号： H04N5/57 , H04N21/4345 , H04N21/4854 , H04N21/84
摘要： An information-processing device receives and processes predetermined program data. The information-processing device includes an extracting unit for extracting image data and audio data of a program selected by a user, an obtaining unit for obtaining information related to the selected program, and a setting unit for setting a control parameter for controlling an image data display or an audio data output of the selected program in accordance with the related information.
摘要翻译：信息处理装置接收并处理预定的节目数据。信息处理装置包括提取单元，用于提取用户选择的节目的图像数据和音频数据，获取单元，用于获得与所选择的节目相关的信息;以及设置单元，用于设置用于控制图像数据的控制参数根据相关信息显示或选择的节目的音频数据输出。

5. 发明授权

US06999129B2 Image processing apparatus, method, and recording medium for controlling image quality 失效
标题翻译：用于控制图像质量的图像处理装置，方法和记录介质
公开(公告)号：US06999129B2
公开(公告)日：2006-02-14
申请号：US09855345
申请日：2001-05-15
申请人： Akira Shirahama , Shinichiro Miyazaki , Hitoshi Nakamura
发明人： Akira Shirahama , Shinichiro Miyazaki , Hitoshi Nakamura
IPC分类号： H04N5/44 , H04N7/00 , H04N7/08 , H04N11/00
CPC分类号： H04N21/443 , H04N5/4401 , H04N19/42 , H04N19/61 , H04N21/42692 , H04N21/4345 , H04N21/44 , H04N21/4854
摘要： Viewing of a program at optimum image quality is realized. A correspondence table of combinations of MPEG video encoding parameters and image signal processing parameters is stored in a RAM. A CPU reads out from the RAM an image signal processing parameter corresponding to a combination of MPEG video encoding parameters supplied from a demultiplexer, and on the basis of the image signal processing parameter, controls image signal processing in an image signal processor.
摘要翻译：实现以最佳图像质量观看节目。将MPEG视频编码参数和图像信号处理参数的组合的对应表存储在RAM中。 CPU从RAM中读出与从解复用器提供的MPEG视频编码参数的组合对应的图像信号处理参数，并且基于图像信号处理参数控制图像信号处理器中的图像信号处理。

6. 发明授权

US06441863B1 Image processing apparatus, image processing method, and television receiver 失效
标题翻译：图像处理装置，图像处理方法和电视接收机
公开(公告)号：US06441863B1
公开(公告)日：2002-08-27
申请号：US09355073
申请日：1999-08-23
申请人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ohno
发明人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ohno
IPC分类号： H04N5445
CPC分类号： H04N5/45 , H04N9/64 , H04N21/4263 , H04N21/4316
摘要： There is provided delay means for allowing a delay difference to be provided between the timing of image size information which is set into writing side memory control means and the timing of image size information which is set into reading side memory control means in a manner such that the image size when data is written into first and second field memories and the image size when the data is read out from the first and the second field memories coincide. The image size information is set into the writing side memory control means and the reading side memory control means so as to have a delay difference between them. The image size is set by controlling the first and the second field memories in accordance with the image size information by the writing side memory control means and the reading side memory control means. A switching control of every field is performed in a manner such that while the writing process is performed to one of the field memories, the reading process is performed to the other field memory.
摘要翻译：提供了延迟装置，用于允许在设置在写入侧存储器控制装置中的图像尺寸信息的定时与设置在读取侧存储器控制装置中的图像尺寸信息的定时之间提供延迟差，当数据被写入第一和第二场存储器时的图像大小以及当从第一和第二场存储器读出数据时的图像大小一致。图像尺寸信息被设置在写入侧存储器控制装置和读取侧存储器控制装置中，以便在它们之间具有延迟差。通过由写入侧存储器控制装置和读取侧存储器控制装置根据图像尺寸信息控制第一和第二场存储器来设置图像尺寸。以这样的方式执行每个场的切换控制，即当对一个场存储器执行写入处理时，对另一场存储器执行读取处理。

7. 发明授权

US06219104B1 Picture processing apparatus and processing method 失效
标题翻译：图像处理装置及处理方法
公开(公告)号：US06219104B1
公开(公告)日：2001-04-17
申请号：US08989586
申请日：1997-12-12
申请人： Akira Shirahama , Shinichiro Miyazaki , Takeshi Ono , Nobuo Ueki
发明人： Akira Shirahama , Shinichiro Miyazaki , Takeshi Ono , Nobuo Ueki
IPC分类号： H04N701
CPC分类号： G06T3/4007
摘要： An interpolation interval Vdp obtained by the picture sizes of the original picture and the converted picture is cumulated by an adder. In the odd field, a selector selects [0.5] as an offset corresponding to an odd/even field determination signal. In the even field, the selector selects [0] as an offset corresponding to the odd/even field determination signal. In a vertical blanking interval, the offset is selected as an output. Thus, in the odd field, the offset value [0.5] is added to the cumulated value of Vdp. Thereafter, Vdp is cumulated again. Corresponding to the cumulated value, a line read address n and linear interpolating coefficients qn1 and qn2 are obtained. When Vdp is cumulated, offsets corresponding to the scanning start points in the odd field and the even field are added. Thus, the interlace accuracy is kept.
摘要翻译：由原始图像和转换图像的图像尺寸获得的插值间隔Vdp由加法器累积。在奇数场中，选择器选择[0.5]作为与奇数/偶数场确定信号相对应的偏移量。在偶数场中，选择器选择[0]作为与奇数/偶数场确定信号相对应的偏移量。在垂直消隐间隔中，选择偏移量作为输出。因此，在奇数场中，偏移值[0.5]被加到Vdp的累积值。此后，再次累积Vdp。对应于累积值，获得行读地址n和线性内插系数qn1和qn2。当Vdp被累积时，相加于奇数场和偶数场中的扫描开始点的偏移量相加。因此，保持隔行精度。

8. 发明授权

US6067124A Image processing apparatus and processing method 失效
标题翻译：图像处理装置及处理方法
公开(公告)号：US6067124A
公开(公告)日：2000-05-23
申请号：US8041
申请日：1998-01-16
申请人： Akira Shirahama , Shinichiro Miyazaki , Takeshi Ohno , Nobuo Ueki
发明人： Akira Shirahama , Shinichiro Miyazaki , Takeshi Ohno , Nobuo Ueki
IPC分类号： H04N5/262 , G06T3/40 , G09G5/36
CPC分类号： G06T3/4007
摘要： When an image size is changed by using a linear interpolating process, a picture quality is improved so as not to overlap the position of an original signal and the position of an interpolation signal. An interpolation interval Vdp which is derived from an original image and an image size after the conversion is stored into a register of an input side and is accumulated and added by an adder from a register of an output side through a selector. A predetermined calculation is performed and an offset value q.sub.0 is obtained in a circuit. The value q.sub.0 is selected by the selector and the register of the output side is initialized for a vertical blanking period. Thus, a value (.delta.+nVdp) in which the value q.sub.0 was added to the accumulation value of Vdp is derived. On the basis of the value (.delta.+nVdp), a read address (n) of the original image and linear interpolation coefficients q.sub.n1 and q.sub.n2 are obtained. A similar process is also executed for the horizonal direction and an address (m) and coefficients p.sub.n1 and p.sub.n2 are obtained. A proper offset value is added to the interpolating position and the picture quality can be improved without overlapping the original signal and the interpolating position.
摘要翻译：当通过使用线性内插处理改变图像尺寸时，改善图像质量，以便不与原始信号的位置和插值信号的位置重叠。从原始图像导出的内插间隔Vdp和转换后的图像尺寸被存储到输入侧的寄存器中，并且通过加法器从输出侧的寄存器通过选择器累加并相加。执行预定的计算，并且在电路中获得偏移值q0。选择器选择值q0，输出侧的寄存器在垂直消隐期间初始化。因此，导出将值q0加到Vdp的累加值的值（delta + nVdp）。基于值（delta + nVdp），获得原始图像的读取地址（n）和线性内插系数qn1和qn2。对于水平方向也执行类似的处理，并且获得地址（m）并且获得系数pn1和pn2。将适当的偏移值添加到内插位置，并且可以改善图像质量，而不会重叠原始信号和内插位置。

9. 发明授权

US6064444A Picture processing apparatus and processing method 失效
标题翻译：图像处理装置及处理方法
公开(公告)号：US6064444A
公开(公告)日：2000-05-16
申请号：US882153
申请日：1997-06-25
申请人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ono , Nobuo Ueki
发明人： Shinichiro Miyazaki , Akira Shirahama , Takeshi Ono , Nobuo Ueki
IPC分类号： G06T3/40 , H04N1/393 , H04N5/14 , H04N5/262 , H04N7/01
CPC分类号： G06T3/4007 , H04N5/14 , H04N5/2628 , H04N5/45 , Y10S348/913
摘要： A picture processing apparatus and method for enlarging and reducing a picture wherein when a picture is reduced, horizontally adjacent pixel data is supplied from a delaying device to a horizontally interpolating circuit. With the pixel data, a coefficient p and a 1's complement (1-p) thereof supplied from an interpolation coefficient circuit, an interpolating process in the horizontal direction is performed. In addition, a pixel at the position of p=1 is thinned out. Pixel data that has been interpolated in the horizontal and vertical directions and that has been thinned out is written to a memory. When a picture is enlarged, pixel data that is read from a memory is delayed by two line memories and two adjacent pixels are properly selected by a switch circuit. A vertically interpolating circuit performs an interpolating process in the vertical direction. When pixel data is read from the memory, particular pixel data is read twice depending on a magnification. In the horizontal direction, likewise, an interpolating process is performed in the similar manner and an enlarging process is performed.
摘要翻译：一种用于放大和缩小图像的图像处理装置和方法，其中当图像被缩小时，水平相邻的像素数据从延迟装置提供给水平内插电路。利用像素数据，执行从内插系数电路提供的系数p和1的补码（1-p），进行水平方向的内插处理。此外，p = 1的位置处的像素被稀疏。在水平和垂直方向上进行了内插并已被稀疏的像素数据被写入存储器。当图像被放大时，从存储器读取的像素数据被两行存储器延迟，并且两个相邻像素被开关电路适当地选择。垂直内插电路在垂直方向上进行内插处理。当从存储器读取像素数据时，根据放大倍率来读取特定像素数据两次。在水平方向上，同样地，以类似的方式执行内插处理，并且执行放大处理。

10. 发明授权

US07123305B2 Image processing apparatus and method, and recording medium 有权
公开(公告)号：US07123305B2
公开(公告)日：2006-10-17
申请号：US09861124
申请日：2001-05-18
申请人： Akira Shirahama , Ken Tamayama , Shinichiro Miyazaki
发明人： Akira Shirahama , Ken Tamayama , Shinichiro Miyazaki
IPC分类号： H04N7/00 , H04N11/00 , H04N7/12 , H04N11/02
CPC分类号： H04H40/18 , H04N5/4401 , H04N21/42692 , H04N21/4382 , H04N21/443
摘要： Viewing of a program is enabled at optimum image quality. A correspondence table of an image signal processing parameter and a combination of TMCC information and transmission errors is stored in a RAM. A CPU reads out an image signal processing parameter corresponding to a combination of TMCC information supplied from an IF demodulator and transmission errors supplied from the IF demodulator, a demultiplexer and an MPEG video decoder from the correspondence table stored in the RAM, and controls signal processing in an image signal processing portion and display processing in an image display portion based on the image signal processing parameter.

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