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1. 发明申请

US20150277968A1 SOFTWARE REPLAYER FOR TRANSACTIONAL MEMORY PROGRAMS 有权
标题翻译：用于实时存储器程序的软件更新程序
公开(公告)号：US20150277968A1
公开(公告)日：2015-10-01
申请号：US14226312
申请日：2014-03-26
申请人： Justin E. Gottschlich , Gilles A. Pokam , Shiliang Hu , Rolf Kassa , Youfeng Wu , Irina Calciu
发明人： Justin E. Gottschlich , Gilles A. Pokam , Shiliang Hu , Rolf Kassa , Youfeng Wu , Irina Calciu
IPC分类号： G06F9/46 , G06F11/36 , G11C7/10
CPC分类号： G06F9/467 , G06F11/34 , G06F11/362 , G06F11/3648
摘要： A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.
摘要翻译：公开了一种包括处理器和动态随机存取存储器（DRAM）的系统。处理器包括包括硬件事务存储器（HTM）的混合事务处理存储器（HyTM），并且使用HyTM执行用于重放包括HTM指令并已被执行的程序的程序调试器。程序调试器包括一个软件仿真器，通过仿真HTM来重播HTM指令。公开和要求保护其他实施例。

2. 发明授权

US09135139B2 Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions 有权
标题翻译：使用表达式在多线程程序中识别和再现并发违规的方法和系统
公开(公告)号：US09135139B2
公开(公告)日：2015-09-15
申请号：US13535334
申请日：2012-06-27
申请人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
发明人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F11/00 , G06F9/45 , G06F3/00 , G06F9/46 , G06F13/00 , G06F11/36
CPC分类号： G06F11/3688 , G06F8/70 , G06F11/36 , G06F11/3632
摘要： Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.
摘要翻译：公开了在多线程程序中识别和再现并发错误的方法和系统。本文公开的示例性方法包括定义数据类型。数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。这种关系在满足时会导致并发错误被检测到。符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

3. 发明授权

US08683243B2 Dynamic core selection for heterogeneous multi-core systems 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US08683243B2
公开(公告)日：2014-03-25
申请号：US13046031
申请日：2011-03-11
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

4. 发明申请

US20120233477A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US20120233477A1
公开(公告)日：2012-09-13
申请号：US13046031
申请日：2011-03-11
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F9/318 , G06F1/32
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

5. 发明申请

US20120079245A1 DYNAMIC OPTIMIZATION FOR CONDITIONAL COMMIT 审中-公开
标题翻译：动态优化条件咨询
公开(公告)号：US20120079245A1
公开(公告)日：2012-03-29
申请号：US12890638
申请日：2010-09-25
申请人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
发明人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3857
摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
摘要翻译：本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。虽然投机检查点能够在中止交易后快速有效地恢复。处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

6. 发明申请

US20110320766A1 APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE 审中-公开
标题翻译：用于提高功率的装置，方法和系统，通过与第二核心类型耦合的第一核心类型的性能效率
公开(公告)号：US20110320766A1
公开(公告)日：2011-12-29
申请号：US12826107
申请日：2010-06-29
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30076 , G06F9/30174 , G06F9/3879 , G06F9/4893 , Y02D10/24
摘要： An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.
摘要翻译：本文描述了一种用于将第一类型的处理器核与第二类型的共同设计的核耦合的装置和方法。对第一个核心上的程序代码执行进行监控，并且识别程序代码的热部分。这些热部分优化用于在共同设计的芯上执行，使得在随后遇到这些热部分时，优化的热部分在共同设计的核上执行。当共同设计的核心正在执行优化的热代码时，第一处理器核心可以处于低功率状态以节省功率或并行执行其他代码。此外，多个冷码线程可以在第一核心上流水线化，而多个热代码线程在共同设计的核心上进行流水线以实现最大性能。

7. 发明申请

US20160116965A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开
公开(公告)号：US20160116965A1
公开(公告)日：2016-04-28
申请号：US14986678
申请日：2016-01-02
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

8. 发明申请

US20140007054A1 METHODS AND SYSTEMS TO IDENTIFY AND REPRODUCE CONCURRENCY VIOLATIONS IN MULTI-THREADED PROGRAMS USING EXPRESSIONS 有权
标题翻译：使用表达法识别并复制多个程序中的同时违反的方法和系统
公开(公告)号：US20140007054A1
公开(公告)日：2014-01-02
申请号：US13535334
申请日：2012-06-27
申请人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
发明人： Youfeng Wu , Justin E. Gottschlich , Gilles Pokam , Shiliang Hu , Ali-Reza Adl-Tabatabai , Cristiano L. Pereira
IPC分类号： G06F11/36
CPC分类号： G06F11/3688 , G06F8/70 , G06F11/36 , G06F11/3632
摘要： Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.
摘要翻译：公开了在多线程程序中识别和再现并发错误的方法和系统。本文公开的示例性方法包括定义数据类型。数据类型包括与第一条件相关联的多线程程序的第一线程相关联的第一谓词，与多线程程序的第二线程相关联的第二谓词，第二谓词与第一谓词相关联第二个条件和一个定义第一个谓词和第二个谓词之间的关系的表达式。这种关系在满足时会导致并发错误被检测到。符合数据类型的并发错误检测器用于检测多线程程序中的并发错误。

9. 发明授权

US08443353B2 Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region 有权
公开(公告)号：US08443353B2
公开(公告)日：2013-05-14
申请号：US12890639
申请日：2010-09-25
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Cheng Wang , Edson Borin , Shiliang Hu , Craig B. Zilles
IPC分类号： G06F9/45
摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

10. 发明申请

US20120054449A1 METHOD AND APPARATUS FOR FUZZY STRIDE PREFETCH 有权
标题翻译： FUZZY STRIDE PREFETCH的方法和装置
公开(公告)号：US20120054449A1
公开(公告)日：2012-03-01
申请号：US12871164
申请日：2010-08-30
申请人： Shiliang Hu , Youfeng Wu
发明人： Shiliang Hu , Youfeng Wu
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/1041 , G06F2212/502 , G06F2212/6024 , G06F2212/6026
摘要： In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一种预取引擎，用于检测存储器中的数据访问步进何时落入一个范围内，以计算预测的下一步，以使用预测的下一步来选择性地预取高速缓存行，并且动态地控制预取。还描述和要求保护其他实施例。

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