专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4941028A Structure for protecting thin dielectrics during processing 失效
标题翻译：用于在加工过程中保护细电介质的结构
公开(公告)号：US4941028A
公开(公告)日：1990-07-10
申请号：US230463
申请日：1988-08-10
申请人： Shih-Ou Chen , John L. McCollum , Steve S. Chiang
发明人： Shih-Ou Chen , John L. McCollum , Steve S. Chiang
IPC分类号： H01L23/60 , H01L27/02
CPC分类号： H01L27/0251 , H01L23/60 , H01L2924/0002
摘要： A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.
摘要翻译：公开了一种用于保护电介质的结构，其中位于电介质附近的晶体管与覆盖脆性电介质的导体串联连接，使得晶体管栅极将与脆性介质上的导电材料一起积聚电荷。在制造之后和在正常的电路操作期间，该晶体管器件保持在断开状态，将脆弱的介电节点与其它电路隔离。在替代实施例中，保护晶体管是浮动栅极耗尽器件，其将始终导通，直到电路被激活。在电路被激活时，通过平行与其相关联的连接点，在栅极上俘获电子来关闭器件。在优选的实施例中，在形成覆盖电介质（通常是多晶硅）的导体之后形成掩埋接触。该埋入触点将导体连接到放电晶体管。或者，电介质中的弱部分可以通过在需要埋入触点的区域内放置轻掺杂的N型扩散来故意地产生。

2. 发明授权

US5412244A Electrically-programmable low-impedance anti-fuse element 失效
标题翻译：电子可编程低阻抗保险丝元件
公开(公告)号：US5412244A
公开(公告)日：1995-05-02
申请号：US54612
申请日：1993-04-29
申请人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCollum , Shih-Ou Chen , Steve S. Chiang
发明人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCollum , Shih-Ou Chen , Steve S. Chiang
IPC分类号： H01L23/525 , H01L29/46 , H01L29/86 , H01L29/92
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： Electrically-programmable low-impedance antifuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or metal having a barrier metal underneath. At least one of the two electrodes of each antifuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer.
摘要翻译：公开了电可编程低阻抗反熔丝，其具有在编程之前具有非常低的泄漏并且在编程之后具有低电阻的电容器状结构。本发明的反熔丝包括可以在半导体衬底中形成为扩散区域的第一导电电极，或者可以由位于衬底上方并与衬底绝缘的半导体材料（例如多晶硅）形成。电介质层设置在第一电极上。第二电极由诸如多晶硅的半导体材料或在其下方具有阻挡金属的金属在电介质层上形成。每个反熔丝的两个电极中的至少一个被高掺杂或注入砷，使得高浓度的砷存在于电极和电介质层之间的界面处。

3. 发明授权

US5111262A Structure for protecting thin dielectrics during processing 失效
标题翻译：用于在加工过程中保护细电介质的结构
公开(公告)号：US5111262A
公开(公告)日：1992-05-05
申请号：US440306
申请日：1989-11-22
申请人： Shih-Ou Chen , John L. McCollum , Steve S. Chiang
发明人： Shih-Ou Chen , John L. McCollum , Steve S. Chiang
IPC分类号： H01L23/60 , H01L27/02
CPC分类号： H01L27/0251 , H01L23/60 , H01L2924/0002
摘要： A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remians in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalanching a junction associated with it. In a preferred embodiment, a buried contact if formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.
摘要翻译：公开了一种用于保护电介质的结构，其中位于电介质附近的晶体管与覆盖脆性电介质的导体串联连接，使得晶体管栅极将与脆性介质上的导电材料一起积聚电荷。在制造之后和在正常的电路操作期间，该晶体管器件重新处于断开状态，将脆弱的介质节点与其它电路隔离。在替代实施例中，保护晶体管是浮动栅极耗尽器件，其将始终导通，直到电路被激活。在电路被激活时，通过将与其相关联的连接点进行雪崩而在栅极上俘获电子来关闭该器件。在优选实施例中，如果形成在覆盖电介质（通常是多晶硅）的导体之后形成掩埋触点。该埋入触点将导体连接到放电晶体管。或者，电介质中的弱部分可以通过在需要埋入触点的区域内放置轻掺杂的N型扩散来故意地产生。

4. 发明授权

US5266829A Electrically-programmable low-impedance anti-fuse element 失效
标题翻译：电子可编程低阻抗保险丝元件
公开(公告)号：US5266829A
公开(公告)日：1993-11-30
申请号：US910422
申请日：1992-07-08
申请人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCullum , Shih-Ou Chen , Steve S. Chiang
发明人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCullum , Shih-Ou Chen , Steve S. Chiang
IPC分类号： H01L23/525 , H01L27/06 , H01L27/08
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the antifuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.
摘要翻译：公开了电可编程的低阻抗抗熔丝，其具有电容器状结构，在编程之前具有非常低的泄漏并且在编程之后具有低电阻。本发明的电可编程低阻抗反熔丝包括可以形成为半导体衬底中的扩散区域的第一导电电极，或者可以由位于衬底上方并与衬底绝缘的半导体材料（例如多晶硅）形成。在优选实施例中，介电层包括第一层二氧化硅，第二层氮化硅和第三层二氧化硅，设置在第一电极上。第二电极由诸如多晶硅的半导体材料或在其下方具有阻挡金属的金属在电介质层上形成。每个反熔丝的两个电极中的至少一个被高度掺杂或注入砷，使得高浓度的砷存在于电极和电介质层之间的界面处。这种砷将与其他材料结合并经编程后流入反熔丝，以形成低电阻可控的反熔丝链。提供电路，其允许通过对包含反熔丝的集成电路的输入输出引脚施加合适的编程电压来编程本发明的反熔丝。在使用输入 - 输出端子上施加的编程电压对多个反熔丝进行编程的情况下，其他附加输入 - 输出端可用作地址输入，以指定要编程的反熔丝。

5. 发明授权

US5070384A Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer 失效
标题翻译：引入电介质和非晶硅层的电可编程抗体元件
公开(公告)号：US5070384A
公开(公告)日：1991-12-03
申请号：US508306
申请日：1990-04-12
申请人： John L. McCollum , Shih-Ou Chen
发明人： John L. McCollum , Shih-Ou Chen
IPC分类号： H01L27/10 , H01L21/8247 , H01L23/525 , H01L23/532 , H01L27/115
CPC分类号： H01L23/5252 , H01L23/53223 , H01L2924/0002 , H01L2924/3011
摘要： An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse.

6. 发明授权

US4786612A Plasma enhanced chemical vapor deposited vertical silicon nitride resistor 失效
标题翻译：等离子体增强化学气相沉积立式氮化硅电阻
公开(公告)号：US4786612A
公开(公告)日：1988-11-22
申请号：US139187
申请日：1987-12-29
申请人： Leopoldo D. Yau , Shih-Ou Chen , Yih S. Lin
发明人： Leopoldo D. Yau , Shih-Ou Chen , Yih S. Lin
IPC分类号： H01L21/02 , H01L27/11 , H01C7/10 , H01L29/04
CPC分类号： H01L28/20 , H01L27/1112 , Y10S148/114 , Y10S148/136
摘要： An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.
摘要翻译：一种用于MOS集成电路的改进型电阻器。在分离两个导电区域的绝缘层中形成开口。钝化材料如富硅氮化硅的等离子体增强化学气相沉积沉积在窗口中，与两个导电区域接触并且在这些区域之间沿垂直方向提供电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式