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1. 发明授权

US08604359B2 Package substrate and fabrication method thereof 有权
标题翻译：封装基板及其制造方法
公开(公告)号：US08604359B2
公开(公告)日：2013-12-10
申请号：US13241264
申请日：2011-09-23
申请人： Tsung-Yuan Chen , Shih-Lian Cheng
发明人： Tsung-Yuan Chen , Shih-Lian Cheng
IPC分类号： H05K1/11
CPC分类号： H05K3/4038 , H01L21/4857 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/83102 , H01L2924/12042 , H01L2924/15311 , H05K3/10 , H05K3/3436 , H05K3/4644 , H05K3/4694 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , H01L2924/014 , H01L2924/00
摘要： A package substrate includes a core board, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core board. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded bump pads are located on an upper surface of the insulating layer.
摘要翻译：封装基板包括芯板，第一介电层，第二电路图案，第一焊料掩模和绝缘层。第一电路图案设置在芯板的第一表面上。第一电介质层覆盖第一电路图案。第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。第一焊接掩模覆盖芯片安装区域外的第二电路图案的一部分。绝缘层覆盖芯片安装区域和互连电路图案。多个嵌入式凸块焊盘位于绝缘层的上表面上。

2. 发明申请

US20120313240A1 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20120313240A1
公开(公告)日：2012-12-13
申请号：US13241285
申请日：2011-09-23
申请人： Shih-Lian Cheng , Tsung-Yuan Chen
发明人： Shih-Lian Cheng , Tsung-Yuan Chen
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81411 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package includes a substrate having a flip chip bonding area. A plurality of recessed bump pads are disposed in the flip chip bonding area. The substrate further includes a solder mask that covers a circuit area. A chip having a plurality of metal bumps is mounted in the flip chip bonding area. The metal bumps are respectively connected to the recessed bump pads. An underfill is filled into the gap between the substrate and the chip.
摘要翻译：半导体封装包括具有倒装芯片接合区域的衬底。多个凹陷凸块焊盘设置在倒装芯片接合区域中。基板还包括覆盖电路区域的焊接掩模。具有多个金属凸块的芯片安装在倒装芯片接合区域中。金属凸块分别连接到凹凸焊盘。将底部填充物填充到基板和芯片之间的间隙中。

3. 发明申请

US20120312584A1 PACKAGE SUBSTRATE AND FABRICATION METHOD THEREOF 有权
标题翻译：封装基板及其制造方法
公开(公告)号：US20120312584A1
公开(公告)日：2012-12-13
申请号：US13241264
申请日：2011-09-23
申请人： Tsung-Yuan Chen , Shih-Lian Cheng
发明人： Tsung-Yuan Chen , Shih-Lian Cheng
IPC分类号： H05K1/02 , H05K3/00
CPC分类号： H05K3/4038 , H01L21/4857 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/83102 , H01L2924/12042 , H01L2924/15311 , H05K3/10 , H05K3/3436 , H05K3/4644 , H05K3/4694 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , H01L2924/014 , H01L2924/00
摘要： A package substrate includes a core board, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core board. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded bump pads are located on an upper surface of the insulating layer.
摘要翻译：封装基板包括芯板，第一介电层，第二电路图案，第一焊料掩模和绝缘层。第一电路图案设置在芯板的第一表面上。第一电介质层覆盖第一电路图案。第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。第一焊接掩模覆盖芯片安装区域外的第二电路图案的一部分。绝缘层覆盖芯片安装区域和互连电路图案。多个嵌入式凸块焊盘位于绝缘层的上表面上。

4. 发明申请

US20090280617A1 FABRICATING PROCESS FOR SUBSTRATE WITH EMBEDDED PASSIVE COMPONENT 有权
标题翻译：具有嵌入式被动元件的基板的制造工艺
公开(公告)号：US20090280617A1
公开(公告)日：2009-11-12
申请号：US12358852
申请日：2009-01-23
申请人： Shih-Lian Cheng
发明人： Shih-Lian Cheng
IPC分类号： H01L21/71
CPC分类号： H05K1/165 , H05K1/092 , H05K1/167 , H05K1/183 , H05K3/427 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/086 , H05K2201/09736 , H05K2201/09881 , H05K2203/1147 , H05K2203/1453
摘要： A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component.
摘要翻译：提供了一种具有嵌入式无源元件的基板的制造工艺。制造过程包括以下步骤。首先，提供包括顶部导电层，底部导电层和至少介电层的基板。顶导电层和底导电层分别设置在电介质层的顶表面和底表面上。接下来，在基板上形成多个电镀通孔。然后，对顶部和底部导电层进行图案化以分别形成图案化的顶部导电层和图案化的底部导电层，并且介电层部分暴露。图案化的顶部导电层和图案化的底部导电层具有许多迹线和由迹线形成的许多沟槽。此后，沟槽填充有材料，其中迹线和材料适于形成无源部件。

5. 发明授权

US07223687B1 Printed wiring board and method of fabricating the same 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US07223687B1
公开(公告)日：2007-05-29
申请号：US11465873
申请日：2006-08-21
申请人： Chung W. Ho , Shih-Lian Cheng , Leo Shen
发明人： Chung W. Ho , Shih-Lian Cheng , Leo Shen
IPC分类号： H01L21/4763
CPC分类号： H05K3/4682 , H05K3/0058 , H05K3/0097 , H05K2203/0152 , H05K2203/1536 , Y10T29/49124 , Y10T29/49126
摘要： A method of fabricating a printed wiring board comprising the following steps is provided. A portion of each of two dielectric layers or metal layers bonds to both sides of a carrier plate, respectively. Two build-up wiring structures are respectively formed on the dielectric layers or the metal layers by a build-up process. The portions of the dielectric layers or metal layers bonded to the carrier plate are removed such that the dielectric layers or metal layers and the build-up wiring structures formed thereon are released from the carrier plate to form two printed wiring boards.
摘要翻译：提供一种制造印刷电路板的方法，包括以下步骤。两个电介质层或金属层中的每一个的一部分分别结合到载体板的两侧。通过堆积工艺在电介质层或金属层上分别形成两个堆叠布线结构。去除与载体板接合的电介质层或金属层的部分，使得形成在其上的电介质层或金属层和积聚线结构从载体板释放以形成两个印刷线路板。

6. 发明申请

US20050282309A1 CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT AND FABRICATION PROCESS THEREOF 失效
标题翻译：具有嵌入式被动元件的电路板及其制造工艺
公开(公告)号：US20050282309A1
公开(公告)日：2005-12-22
申请号：US10908987
申请日：2005-06-03
申请人： Shih-Lian Cheng
发明人： Shih-Lian Cheng
IPC分类号： H01L21/44 , H01L21/48 , H05K1/16 , H05K3/06
CPC分类号： H01L21/4857 , H05K1/162 , H05K1/167 , H05K3/064 , H05K2201/0355 , H05K2201/09763 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49131 , Y10T29/49155
摘要： A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material layer is formed on the first surface. A circuit unit including second through holes is provided. Locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the circuit unit are aligned by the first through holes and the second through holes, while the first surface of the conductive layer faces the circuit unit, and the passive component material layer is between the circuit unit and the conductive layer. The conductive layer is laminated to the circuit unit. The conductive layer is patterning to form a circuit layer.
摘要翻译：提供了一种用于制造具有嵌入式无源元件的电路板的工艺。提供包括与第一表面相对的第一表面和第二表面的导电层。导电层分别具有穿过导电层的第一通孔。在第一表面上形成至少一个无源部件材料层。提供包括第二通孔的电路单元。第二通孔的位置分别对应于第一通孔的位置。导电层和电路单元通过第一通孔和第二通孔排列，而导电层的第一表面面向电路单元，无源元件材料层位于电路单元和导电层之间。导电层被层压到电路单元上。导电层被图案化以形成电路层。

7. 发明授权

US07674672B2 Fabricating process for substrate with embedded passive component 有权
标题翻译：具有嵌入式无源元件的基板的制造工艺
公开(公告)号：US07674672B2
公开(公告)日：2010-03-09
申请号：US12358852
申请日：2009-01-23
申请人： Shih-Lian Cheng
发明人： Shih-Lian Cheng
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/20 , H01L21/44
CPC分类号： H05K1/165 , H05K1/092 , H05K1/167 , H05K1/183 , H05K3/427 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/086 , H05K2201/09736 , H05K2201/09881 , H05K2203/1147 , H05K2203/1453
摘要： A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component.
摘要翻译：提供了一种具有嵌入式无源元件的基板的制造工艺。制造过程包括以下步骤。首先，提供包括顶部导电层，底部导电层和至少介电层的基板。顶导电层和底导电层分别设置在电介质层的顶表面和底表面上。接下来，在基板上形成多个电镀通孔。然后，对顶部和底部导电层进行图案化以分别形成图案化的顶部导电层和图案化的底部导电层，并且介电层部分暴露。图案化的顶部导电层和图案化的底部导电层具有许多迹线和由迹线形成的许多沟槽。此后，沟槽填充有材料，其中迹线和材料适于形成无源部件。

8. 发明申请

US20090196979A1 INKJET PRINTING PROCESS FOR CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板印刷工艺
公开(公告)号：US20090196979A1
公开(公告)日：2009-08-06
申请号：US12208636
申请日：2008-09-11
申请人： Shih-Lian Cheng , Hung-Sen Wei
发明人： Shih-Lian Cheng , Hung-Sen Wei
IPC分类号： H05K3/06
CPC分类号： H05K3/061 , H05K3/0079 , H05K3/382 , H05K3/383 , H05K2203/013 , H05K2203/025
摘要： An inkjet printing process for a circuit board includes the following procedures. Firstly, a substrate and a conductive layer disposed on the substrate are provided. Afterward, a roughening treatment is performed on the conductive layer so that the roughness of the conductive layer is between 0.1 μm and 5 μm. Then, a patterned mask layer is printed on the conductive layer for covering an area of the conductive layer prepared for forming a circuit pattern.
摘要翻译：电路板的喷墨印刷方法包括以下步骤。首先，提供设置在基板上的基板和导电层。之后，对导电层进行粗糙化处理，使得导电层的粗糙度在0.1μm和5μm之间。然后，在导电层上印刷图案化的掩模层，以覆盖为形成电路图案而准备的导电层的区域。

9. 发明授权

US07441329B2 Fabrication process circuit board with embedded passive component 失效
标题翻译：具有嵌入式无源元件的制造工艺电路板
公开(公告)号：US07441329B2
公开(公告)日：2008-10-28
申请号：US10908987
申请日：2005-06-03
申请人： Shih-Lian Cheng
发明人： Shih-Lian Cheng
IPC分类号： H01R43/00
CPC分类号： H01L21/4857 , H05K1/162 , H05K1/167 , H05K3/064 , H05K2201/0355 , H05K2201/09763 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49131 , Y10T29/49155
摘要： A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material layer is formed on the first surface. A circuit unit including second through holes is provided. Locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the circuit unit are aligned by the first through holes and the second through holes, while the first surface of the conductive layer faces the circuit unit, and the passive component material layer is between the circuit unit and the conductive layer. The conductive layer is laminated to the circuit unit. The conductive layer is patterning to form a circuit layer.
摘要翻译：提供了一种用于制造具有嵌入式无源元件的电路板的工艺。提供包括与第一表面相对的第一表面和第二表面的导电层。导电层分别具有穿过导电层的第一通孔。在第一表面上形成至少一个无源部件材料层。提供包括第二通孔的电路单元。第二通孔的位置分别对应于第一通孔的位置。导电层和电路单元通过第一通孔和第二通孔排列，而导电层的第一表面面向电路单元，无源元件材料层位于电路单元和导电层之间。导电层被层压到电路单元上。导电层被图案化以形成电路层。

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