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1. 发明申请

US20120300550A1 Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation 有权
标题翻译：缓存通过电压，以增强存储器件中的通道升压，具有可选的温度补偿
公开(公告)号：US20120300550A1
公开(公告)日：2012-11-29
申请号：US13113786
申请日：2011-05-23
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

2. 发明授权

US08526233B2 Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation 有权
标题翻译：斜坡通过电压可增强存储器件的通道升压，并可选择温度补偿
公开(公告)号：US08526233B2
公开(公告)日：2013-09-03
申请号：US13113786
申请日：2011-05-23
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

3. 发明授权

US08472266B2 Reducing neighbor read disturb 有权
标题翻译：减少邻居读取干扰
公开(公告)号：US08472266B2
公开(公告)日：2013-06-25
申请号：US13077778
申请日：2011-03-31
申请人： Anubhav Khandelwal , Jun Wan , Shih-Chung Lee , Dana Lee
发明人： Anubhav Khandelwal , Jun Wan , Shih-Chung Lee , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.
摘要翻译：公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

4. 发明申请

US20120250414A1 REDUCING NEIGHBOR READ DISTURB 有权
标题翻译：减少邻居阅读障碍
公开(公告)号：US20120250414A1
公开(公告)日：2012-10-04
申请号：US13077778
申请日：2011-03-31
申请人： Anubhav Khandelwal , Jun Wan , Shih-Chung Lee , Dana Lee
发明人： Anubhav Khandelwal , Jun Wan , Shih-Chung Lee , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.
摘要翻译：公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

5. 发明申请

US20110286279A1 Erase and Programming Techniques to Reduce the Widening of State Distributions in Non-Volatile Memories 有权
标题翻译：擦除和编程技术来减少非易失性存储器中状态分布的扩大
公开(公告)号：US20110286279A1
公开(公告)日：2011-11-24
申请号：US13072387
申请日：2011-03-25
申请人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
发明人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
IPC分类号： G11C16/10 , G11C16/16
CPC分类号： G11C16/16 , G11C16/3404
摘要： Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
摘要翻译：提供了用于存储器件的技术，以通过减少在多个写入/擦除周期之后发生的状态分布的扩大来提高可靠性和耐久性。一组技术使用预处理操作，其中可以包括程序和温和擦除的脉冲序列被施加到一个或多个字线，同时在字线方向，位线方向或两者上施加电压差。另一组技术使用双脉冲或多脉冲程序过程，其中在一对的第一脉冲中使用增加的字线对字线差分。

6. 发明授权

US08416624B2 Erase and programming techniques to reduce the widening of state distributions in non-volatile memories 有权
标题翻译：擦除和编程技术来减少非易失性存储器中状态分布的扩大
公开(公告)号：US08416624B2
公开(公告)日：2013-04-09
申请号：US13072387
申请日：2011-03-25
申请人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
发明人： Bo Lei , Guirong Liang , Anubhav Khandelwal , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/3404
摘要： Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
摘要翻译：提供了用于存储器件的技术，以通过减少在多个写入/擦除周期之后发生的状态分布的扩大来提高可靠性和耐久性。一组技术使用预处理操作，其中可以包括程序和温和擦除的脉冲序列被施加到一个或多个字线，同时在字线方向，位线方向或两者上施加电压差。另一组技术使用双脉冲或多脉冲程序过程，其中在一对的第一脉冲中使用增加的字线对字线差分。

7. 发明授权

US07907449B2 Two pass erase for non-volatile storage 有权
标题翻译：两路擦除用于非易失性存储
公开(公告)号：US07907449B2
公开(公告)日：2011-03-15
申请号：US12421098
申请日：2009-04-09
申请人： Dana Lee , Nima Mokhlesi , Anubhav Khandelwal
发明人： Dana Lee , Nima Mokhlesi , Anubhav Khandelwal
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C11/5635
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：本文公开了用于擦除非易失性存储器单元的技术。使用试验擦除脉冲擦除存储单元。基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。第二个擦除脉冲用于擦除存储单元。在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。可以执行第二次擦除之后的软编程。可以基于试用擦除脉冲来确定软编程脉冲的幅度。在一个实现中，在软编程之后，不会验证存储单元的阈值电压。限制擦除脉冲数和软编程脉冲可节省时间和功率。确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

8. 发明申请

US20100277983A1 Two Pass Erase For Non-Volatile Storage 有权
标题翻译：双通道擦除非易失性存储
公开(公告)号：US20100277983A1
公开(公告)日：2010-11-04
申请号：US12835423
申请日：2010-07-13
申请人： Nima Mokhlesi , Dana Lee , Anubhav Khandelwal
发明人： Nima Mokhlesi , Dana Lee , Anubhav Khandelwal
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/107 , G11C16/3404 , G11C16/344 , G11C2211/5621
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：本文公开了用于擦除非易失性存储器单元的技术。存储器单元的子集在擦除之前被预处理。预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。作为示例，沿着单个字线的存储器单元可以被预处理。在预处理之后，使用试写擦除脉冲擦除存储单元。基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。第二个擦除脉冲用于擦除存储单元。确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

9. 发明授权

US08264890B2 Two pass erase for non-volatile storage 有权
标题翻译：两路擦除用于非易失性存储
公开(公告)号：US08264890B2
公开(公告)日：2012-09-11
申请号：US12835423
申请日：2010-07-13
申请人： Nima Mokhlesi , Dana Lee , Anubhav Khandelwal
发明人： Nima Mokhlesi , Dana Lee , Anubhav Khandelwal
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/107 , G11C16/3404 , G11C16/344 , G11C2211/5621
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：本文公开了用于擦除非易失性存储器单元的技术。存储器单元的子集在擦除之前被预处理。预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。作为示例，沿着单个字线的存储器单元可以被预处理。在预处理之后，使用试写擦除脉冲擦除存储单元。基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。第二个擦除脉冲用于擦除存储单元。确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

10. 发明申请

US20100259987A1 Two Pass Erase For Non-Volatile Storage 有权
标题翻译：双通道擦除非易失性存储
公开(公告)号：US20100259987A1
公开(公告)日：2010-10-14
申请号：US12421098
申请日：2009-04-09
申请人： Dana Lee , Nima Mokhlesi , Anubhav Khandelwal
发明人： Dana Lee , Nima Mokhlesi , Anubhav Khandelwal
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16 , G11C11/5635
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：本文公开了用于擦除非易失性存储器单元的技术。使用试验擦除脉冲擦除存储单元。基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。第二个擦除脉冲用于擦除存储单元。在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。可以执行第二次擦除之后的软编程。可以基于试用擦除脉冲来确定软编程脉冲的幅度。在一个实现中，在软编程之后，不会验证存储单元的阈值电压。限制擦除脉冲数和软编程脉冲可节省时间和功率。确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

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