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1. 发明授权

US5896501A Multiprocessor system and parallel processing method for processing data transferred between processors 失效
标题翻译：用于处理数据之间传输的多处理器系统和并行处理方法
公开(公告)号：US5896501A
公开(公告)日：1999-04-20
申请号：US795689
申请日：1997-02-04
申请人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
发明人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
IPC分类号： G06F12/10 , G06F12/02 , G06F12/06 , G06F15/16 , G06F15/17 , G06F15/177 , G06F15/167
CPC分类号： G06F12/1072 , G06F12/0284 , G06F12/0692 , G06F15/17
摘要： A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.
摘要翻译：一种用于处理在具有存储器的多个处理器之间传送的数据的并行处理装置和方法。多个处理器中的每一个对应于全局虚拟存储器空间中的全局虚拟地址，其中执行多个处理器之间的并行处理以及执行其中一个处理器中的单独进程的本地虚拟存储器空间中的本地虚拟地址到相同的真实地址。通过根据第二处理器的全局虚拟地址或本地虚拟地址将数据写入第二处理器的存储器中，将数据从多个处理器中的第一处理器传送到多个处理器中的第二处理器，第二处理器处理器被通知全局虚拟地址或传送数据的本地虚拟地址，然后将所通知的全局虚拟地址或通知的本地虚拟地址转换成对应于通知的全局虚拟地址或通知的本地虚拟地址的实际地址根据转换的实际地址将数据从第二处理器的存储器读取到第二处理器，并且在第二处理器中计算读取的数据。

2. 发明授权

US5832261A Barrier synchronizing mechanism for a parallel data processing control system 失效
标题翻译：一种并行数据处理控制系统的屏障同步机制
公开(公告)号：US5832261A
公开(公告)日：1998-11-03
申请号：US983075
申请日：1992-11-30
申请人： Kenichi Ishizaka , Masayuki Katori , Masayuki Ikeda , Shigeru Nagasawa , Hiroshi Komatsuda
发明人： Kenichi Ishizaka , Masayuki Katori , Masayuki Ikeda , Shigeru Nagasawa , Hiroshi Komatsuda
IPC分类号： G06F15/16 , G06F9/44 , G06F9/52 , G06F15/177 , G06F15/80
CPC分类号： G06F8/45 , G06F15/8007
摘要： In a parallel data processing control system for a parallel computer system having a plurality of computers and an adapter device connecting the computers to each other, a first unit, which is provided in the adapter device, transfers pieces of data processing progress state information to the computers. The pieces of the data processing progress state information respectively indicate data processing progress states of the computers. A second unit, which is provided in each of the computers, holds the pieces of the data processing progress state information. A third unit, which is provided in each of the computers, holds management information indicating a group of computers which share a data process. A fourth unit, which is provided in each of the computers, determines whether or not the computers in the group have completed the data process on the basis of the pieces of the data processing progress state information and the management information.
摘要翻译：在具有多个计算机的并行计算机系统和将计算机彼此连接的适配器装置的并行数据处理控制系统中，设置在适配器装置中的第一单元将数据处理进度状态信息传送到电脑。数据处理进度状态信息分别表示计算机的数据处理进度状态。设置在每个计算机中的第二单元保存数据处理进度状态信息。设置在每个计算机中的第三单元保存指示共享数据处理的一组计算机的管理信息。设置在每台计算机中的第四单元基于数据处理进度状态信息和管理信息来确定组中的计算机是否已经完成数据处理。

3. 发明授权

US4143330A Detector circuit 失效
标题翻译：检测电路
公开(公告)号：US4143330A
公开(公告)日：1979-03-06
申请号：US857763
申请日：1977-12-05
申请人： Shigeru Nagasawa
发明人： Shigeru Nagasawa
IPC分类号： H03D1/06 , H03D1/10 , H03D1/18
CPC分类号： H03D1/10 , H03D1/06
摘要： A detector circuit comprising a detector element which includes a diode having a high-frequency input terminal which receives a predetermined DC bias voltage, and a parallel circuit constituted by a resistor and a capacitor and connected between the output terminal of the detector element and a ground terminal. The detector circuit is further provided with a resistor connected between the parallel circuit and the output terminal of the detector element.

4. 发明授权

US5592628A Data communication system which guarantees at a transmission station the arrival of transmitted data to a receiving station and method thereof 失效
标题翻译：数据通信系统，在传输站保证发送数据到达接收站及其方法
公开(公告)号：US5592628A
公开(公告)日：1997-01-07
申请号：US595505
申请日：1996-02-01
申请人： Haruhiko Ueno , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Ken-ichi Ishizaka , Teruo Utsumi , Masami Dewa , Kazushige Kobayakawa
发明人： Haruhiko Ueno , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Ken-ichi Ishizaka , Teruo Utsumi , Masami Dewa , Kazushige Kobayakawa
IPC分类号： G06F9/46 , G06F12/08 , G06F15/173 , H04L12/70 , H04L29/06 , G06F15/163
CPC分类号： G06F9/544 , G06F12/0813 , G06F15/17375
摘要： Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.
摘要翻译：多个处理器元件中的任何两个通过具有确定的通信缓冲器长度并包括多个通信缓冲器的数据通信网络相互耦合。使用处理的数据创建具有报头和主体的分组，然后由发送单元传送。在发送处理后的数据之后，发送单元将具有比数据通信网络中的通信缓冲器长度长的身体的虚拟数据发送到与发送处理后的数据相同的接收站。然后，发送单元保证作为接收站的处理器元件到达先前处理的数据和报头。表示缓存无效等待的控制数据被嵌入到伪数据的头部。当发送端终止虚拟数据的传送时，发送站可以保证由用作接收站的处理器元件执行的高速缓存无效的终止，以达到先前存储数据主存储和高速缓存的内容的一致性记忆。

5. 发明授权

US5557744A Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors 失效
标题翻译：包括传送队列的多处理器系统和用于控制多个处理器之间的数据传送的中断处理单元
公开(公告)号：US5557744A
公开(公告)日：1996-09-17
申请号：US104482
申请日：1993-07-28
申请人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
发明人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
IPC分类号： G06F15/16 , G06F9/54 , G06F13/24 , G06F15/17 , G06F15/177 , G06F13/00
CPC分类号： G06F15/17 , G06F13/24
摘要： A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfer request, and outputs an enqueuing request to the enqueuing unit to realize the interrupt request.
摘要翻译：多处理器系统具有通过网络彼此并行连接的多个处理器，用于执行相互通信。每个处理器包括用于存储传送请求的传送队列单元，主存储器，用于从另一个处理器接收传送请求的接收单元，以及当传送请求在传送队列单元中排队时将指定数据发送到另一个处理器的传输单元。每个处理器还包括第一寄存器，用于存储指示传输队列单元是否已满的信息，即具有可用于存储传送请求的区域;以及第二寄存器，用于在接收操作期间指示传输请求是否为有效传送请求。保存单元连接到接收单元以暂时保存传送请求，并且提供了一个进入单元，用于将从保存单元传送请求排队到传送队列单元。中断处理单元从接收单元接收中断请求，监视传送队列单元的空/满状态，即监视传输队列单元是否具有可用于存储传送请求的区域，并且向入队队列输出入队请求单元实现中断请求。

6. 发明授权

US4467226A Darlington complementary circuit for preventing zero crossover distortion 失效
标题翻译：达林顿互补电路，用于防止零交叉失真
公开(公告)号：US4467226A
公开(公告)日：1984-08-21
申请号：US288797
申请日：1981-07-31
申请人： Shigeru Nagasawa
发明人： Shigeru Nagasawa
IPC分类号： H03F3/30 , H03F3/20 , H03K17/615 , H03K17/66 , H03K3/26 , H03K17/60
CPC分类号： H03K17/615 , H03K17/666
摘要： A Darlington complementary circuit including first and second signal channel Darlington pairs each of which pair has an input and output transistor, wherein a diode is coupled in series with the base-emitter path of the output transistor of each pair to assure simultaneous turn-off of the transistors of each pair, and thereby prevent distortion of an output signal as one pair ceases operation and the other pair begins operation.
摘要翻译：一种达林顿互补电路，包括第一和第二信号通道达林顿对，其中每对具有输入和输出晶体管，其中二极管与每对输出晶体管的基极 - 发射极路径串联耦合以确保同时关断每对晶体管，从而防止一对输出信号失真，另一对开始工作。

7. 发明授权

US5661205A Method for producing a polychloroprene latex 失效
公开(公告)号：US5661205A
公开(公告)日：1997-08-26
申请号：US588389
申请日：1996-01-18
申请人： Mikitoshi Satoh , Masao Koga , Shigeru Nagasawa , Kunihiko Asano , Toshiyuki Uenoyama , Kunihiro Onishi
发明人： Mikitoshi Satoh , Masao Koga , Shigeru Nagasawa , Kunihiko Asano , Toshiyuki Uenoyama , Kunihiro Onishi
IPC分类号： C08F236/18 , C09J111/02 , C09J113/02 , C08K5/06
CPC分类号： C09J111/02 , C08F236/18 , C09J113/02
摘要： A method for producing a polychloroprene latex, which comprises copolymerizing chloroprene and an ethylenically unsaturated carboxylic acid in the presence of a polyvinyl alcohol, wherein a glycol ether is also present during the copolymerization.

8. 发明授权

US5652905A Data processing unit 失效
标题翻译：数据处理单元
公开(公告)号：US5652905A
公开(公告)日：1997-07-29
申请号：US463926
申请日：1995-06-05
申请人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
发明人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
IPC分类号： G06F15/16 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.
摘要翻译：数据处理单元适于经由网络与另一数据处理单元交换数据。数据处理单元包括用于存储程序和数据的主存储器，用于通过执行存储在主存储器中的程序来发布传送请求的指令处理器和用于将从指令处理器传送请求排入传送请求队列的传送处理器，以及用于基于从传送请求队列获得的每个传送请求在主存储器和网络之间执行传送处理。传送处理器包括用于在每个传送请求的传送处理期间发生故障时显示故障的故障显示，来自指令处理器的故障显示的内容的引用和擦除是可能的。在故障显示中显示故障的时间内禁止转移请求队列中传入请求的传送过程。

9. 发明授权

US5572680A Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number 失效
标题翻译：用于处理和传送数据到与目的地逻辑处理器号对应的处理器和/或相应虚拟处理器的方法和装置
公开(公告)号：US5572680A
公开(公告)日：1996-11-05
申请号：US109598
申请日：1993-08-20
申请人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
发明人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
IPC分类号： G06F9/54 , G06F9/46 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.
摘要翻译：在多处理器系统中，传送处理部分允许在多个处理器之间传送数据和系统信息，以便处理器执行并行处理。该系统包括其中实现虚拟处理器的物理处理器和与待处理的多个处理相对应的多个逻辑处理器。在传送数据和系统信息时，每个传送处理部分选择与要传送的处理相对应的目的地逻辑处理号码，并从主存储物理处理器和物理处理器虚拟处理器号码读取对应于逻辑处理器号码，数据以及用于传送到目的地的系统信息。在目的地，物理或虚拟处理器执行该过程。

10. 发明授权

US4293941A Memory access control system in vector processing system 失效
标题翻译：矢量处理系统中的存储器访问控制系统
公开(公告)号：US4293941A
公开(公告)日：1981-10-06
申请号：US40994
申请日：1979-05-21
申请人： Takatoshi Muraoka , Keiichiro Uchida , Minoru Koshino , Masanori Motegi , Shigeru Nagasawa
发明人： Takatoshi Muraoka , Keiichiro Uchida , Minoru Koshino , Masanori Motegi , Shigeru Nagasawa
IPC分类号： G06F12/00 , G06F7/78 , G06F12/06 , G06F12/08 , G06F12/12 , G06F13/16 , G06F15/78 , G06F17/16 , G06F13/00
CPC分类号： G06F7/785 , G06F13/16 , G06F15/8076
摘要： A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.
摘要翻译：矢量处理系统中的存储器访问控制系统包括存储器单元，存储器件，地址保持寄存器，移位寄存器和数据缓冲寄存器。存储器访问控制系统通过移位寄存器的输出，基于地址保持寄存器来区分从存储器单元读出的每个向量数据。移位寄存器存储由存储器件指示的矢量元件号，并将其传送到数据缓冲寄存器。由n个元素a0，a1，a2，...构成的矢量A的0到n-1的每个数。。。 a-1是矢量元素号，从a0到a-1的每个数据是向量元素数据。

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