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1. 发明授权

US5896501A Multiprocessor system and parallel processing method for processing data transferred between processors 失效
标题翻译：用于处理数据之间传输的多处理器系统和并行处理方法
公开(公告)号：US5896501A
公开(公告)日：1999-04-20
申请号：US795689
申请日：1997-02-04
申请人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
发明人： Masayuki Ikeda , Shigeru Nagasawa , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Naoki Sueyasu , Kenichi Ishizaka , Masami Dewa , Moriyuki Takamura
IPC分类号： G06F12/10 , G06F12/02 , G06F12/06 , G06F15/16 , G06F15/17 , G06F15/177 , G06F15/167
CPC分类号： G06F12/1072 , G06F12/0284 , G06F12/0692 , G06F15/17
摘要： A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.
摘要翻译：一种用于处理在具有存储器的多个处理器之间传送的数据的并行处理装置和方法。多个处理器中的每一个对应于全局虚拟存储器空间中的全局虚拟地址，其中执行多个处理器之间的并行处理以及执行其中一个处理器中的单独进程的本地虚拟存储器空间中的本地虚拟地址到相同的真实地址。通过根据第二处理器的全局虚拟地址或本地虚拟地址将数据写入第二处理器的存储器中，将数据从多个处理器中的第一处理器传送到多个处理器中的第二处理器，第二处理器处理器被通知全局虚拟地址或传送数据的本地虚拟地址，然后将所通知的全局虚拟地址或通知的本地虚拟地址转换成对应于通知的全局虚拟地址或通知的本地虚拟地址的实际地址根据转换的实际地址将数据从第二处理器的存储器读取到第二处理器，并且在第二处理器中计算读取的数据。

2. 发明授权

US5625846A Transfer request queue control system using flags to indicate transfer request queue validity and whether to use round-robin system for dequeuing the corresponding queues 失效
标题翻译：传输请求队列控制系统使用标志来指示传输请求队列的有效性以及是否使用循环系统对出队的相应队列
公开(公告)号：US5625846A
公开(公告)日：1997-04-29
申请号：US166100
申请日：1993-12-14
申请人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
发明人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
IPC分类号： G06F9/54 , G06F13/38 , G06F15/17 , G06F15/173 , G06F13/00 , G06F13/14
CPC分类号： G06F15/17
摘要： A transfer request queue control system for a parallel computer system includes a plurality of processing units each having a main storage storing instructions and data. An instruction processor reads the instructions from the main storage and executes the instructions. A transfer processor performs data transfers in packets, each comprising a header and body data and each data transfer comprising one or more packets. A network couples transmitting and receiving processing units, which are to perform a data transfer based on information included in the header of each packet, the header information being related to a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor performs parallel processing by making a data transfer between the main storage and the network in successive packets, depending on the attribute of the memory access. The transfer processor of one of the processing units comprises a transfer request queue comprising a list of headers of respective packets corresponding to each of plural requested data transfers, a managing part for managing a transfer queue valid flag which indicates validity of a transfer request of the transfer request queue and a control part for performing a data transfer in response to a data transfer request and based on the transfer queue valid flag.
摘要翻译：用于并行计算机系统的传送请求队列控制系统包括多个处理单元，每个处理单元具有存储指令和数据的主存储器。指令处理器从主存储器读取指令并执行指令。传送处理器执行分组中的数据传输，每个数据包括报头和主体数据，并且每个数据传输包括一个或多个分组。网络耦合发送和接收处理单元，其将基于包括在每个分组的报头中的信息执行数据传输，与数据的目的地相关的报头信息，对主存储器的存储器访问的属性以及数据长度。转移处理器通过根据存储器访问的属性在连续的分组中进行主存储和网络之间的数据传送来执行并行处理。处理单元之一的传送处理器包括传送请求队列，其包括与多个请求的数据传送中的每一个对应的各个分组的标题的列表，用于管理传送队列有效标志的管理部分，其指示传输请求的转发请求的有效性传送请求队列和用于响应于数据传输请求并基于传输队列有效标志执行数据传输的控制部分。

3. 发明授权

US5592680A Abnormal packet processing system 失效
标题翻译：异常包处理系统
公开(公告)号：US5592680A
公开(公告)日：1997-01-07
申请号：US391085
申请日：1995-02-21
申请人： Teruo Utsumi , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
发明人： Teruo Utsumi , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
IPC分类号： G06F13/00 , G06F15/173 , H04L12/26 , G06F11/00
CPC分类号： H04L43/00 , H04L12/26
摘要： This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.
摘要翻译：本发明涉及异常分组处理系统，其目的在于通过接收处理器在多个处理单元之间的通信期间最小化异常分组的处理。该数据处理系统包括通过互连连接的多个处理单元。处理单元中的至少一个是发送处理器，其包括用于在将数据分组发送到接收处理器期间检测数据分组的异常的单元; 以及用于向正在发送的数据分组添加异常报告数据的单元，并将具有异常报告数据的数据分组发送到接收处理器，或者替代地，禁止异常分组的传输。

4. 发明授权

US5652905A Data processing unit 失效
标题翻译：数据处理单元
公开(公告)号：US5652905A
公开(公告)日：1997-07-29
申请号：US463926
申请日：1995-06-05
申请人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
发明人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
IPC分类号： G06F15/16 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.
摘要翻译：数据处理单元适于经由网络与另一数据处理单元交换数据。数据处理单元包括用于存储程序和数据的主存储器，用于通过执行存储在主存储器中的程序来发布传送请求的指令处理器和用于将从指令处理器传送请求排入传送请求队列的传送处理器，以及用于基于从传送请求队列获得的每个传送请求在主存储器和网络之间执行传送处理。传送处理器包括用于在每个传送请求的传送处理期间发生故障时显示故障的故障显示，来自指令处理器的故障显示的内容的引用和擦除是可能的。在故障显示中显示故障的时间内禁止转移请求队列中传入请求的传送过程。

5. 发明授权

US5572680A Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number 失效
标题翻译：用于处理和传送数据到与目的地逻辑处理器号对应的处理器和/或相应虚拟处理器的方法和装置
公开(公告)号：US5572680A
公开(公告)日：1996-11-05
申请号：US109598
申请日：1993-08-20
申请人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
发明人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
IPC分类号： G06F9/54 , G06F9/46 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.
摘要翻译：在多处理器系统中，传送处理部分允许在多个处理器之间传送数据和系统信息，以便处理器执行并行处理。该系统包括其中实现虚拟处理器的物理处理器和与待处理的多个处理相对应的多个逻辑处理器。在传送数据和系统信息时，每个传送处理部分选择与要传送的处理相对应的目的地逻辑处理号码，并从主存储物理处理器和物理处理器虚拟处理器号码读取对应于逻辑处理器号码，数据以及用于传送到目的地的系统信息。在目的地，物理或虚拟处理器执行该过程。

6. 发明授权

US5822785A Data transfer using local and global address translation and authorization 失效
标题翻译：使用本地和全球地址转换和授权进行数据传输
公开(公告)号：US5822785A
公开(公告)日：1998-10-13
申请号：US951295
申请日：1997-10-16
申请人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
发明人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
IPC分类号： G06F12/02 , G06F12/10 , G06F12/14 , G06F15/16 , G06F15/167 , G06F15/17 , G06F15/177
CPC分类号： G06F12/0284 , G06F12/1036 , G06F12/1072 , G06F12/1475 , G06F15/17
摘要： A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access information to data. The system information storage section stores space identifying information for identifying each of plural kinds of virtual spaces allocated according to applications of the storages. A plurality of address translation sections translate virtual addresses into real addresses, corresponding to the plural kinds of virtual spaces on the basis of the access information. A selection section selects any one of the plurality of address translation sections on the basis of the space identifying information. A transfer control section reads the data of the storage on the basis of the real address obtained by the selected address translation section and transfers the data to other processors together with the access information and the space identifying information.
摘要翻译：系统信息存储部分存储访问信息，该访问信息表示通过将访问信息与数据相关联来访问处理器特有的存储器和其他处理器所特有的存储的属性。系统信息存储部存储用于识别根据存储器的应用分配的多种虚拟空间中的每一种的空间识别信息。多个地址转换部分根据访问信息将虚拟地址转换为与多种虚拟空间对应的实际地址。选择部分基于空间识别信息来选择多个地址转换部分中的任何一个。传送控制部分基于由所选地址转换部分获得的实际地址读取存储器的数据，并将数据与访问信息和空格识别信息一起传送到其他处理器。

7. 发明授权

US5664104A Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unit 失效
标题翻译：包括多个故障显示单元的传送处理器，其中如果在故障显示单元中指示了故障，则禁止传送处理
公开(公告)号：US5664104A
公开(公告)日：1997-09-02
申请号：US166929
申请日：1993-12-15
申请人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
发明人： Naoki Shinjo , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Teruo Utsumi , Kazushige Kobayakawa , Masami Dewa , Kenichi Ishizaka , Tadao Amada
IPC分类号： G06F15/16 , G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.
摘要翻译：数据处理单元适于经由网络与另一数据处理单元交换数据。数据处理单元包括用于存储程序和数据的主存储器，用于通过执行存储在主存储器中的程序来发布传送请求的指令处理器和用于将从指令处理器传送请求排入传送请求队列的传送处理器，以及用于基于从传送请求队列获得的每个传送请求在主存储器和网络之间执行传送处理。传送处理器包括用于在每个传送请求的传送处理期间发生故障时显示故障的故障显示，来自指令处理器的故障显示的内容的引用和擦除是可能的。在故障显示中显示故障的时间内禁止转移请求队列中传入请求的传送过程。

8. 发明授权

US5634071A Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel 失效
标题翻译：用于并行执行多个程序的多个处理器的同步处理方法和装置
公开(公告)号：US5634071A
公开(公告)日：1997-05-27
申请号：US601705
申请日：1996-02-15
申请人： Masami Dewa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Kenichi Ishizaka , Moriyuki Takamura
发明人： Masami Dewa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Kazushige Kobayakawa , Kenichi Ishizaka , Moriyuki Takamura
IPC分类号： G06F15/16 , G06F9/45 , G06F9/52 , G06F15/177 , G06F9/00
CPC分类号： G06F8/458
摘要： A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information. A processing shifting element shifts, when the group of processors are judged to be in synchronism, all the processors in the group to the next process of a program.
摘要翻译：一种包括多个处理器和通信网络的同步处理系统。每个处理器包括同步组合存储元件，状态存储元件，控制元件，判断元件和移位元件。同步组合存储单元存储表示在并行执行程序期间同步的一组处理器的同步组合信息。同步状态存储单元存储指示在处理器完成其处理之后到达同步等待状态的同步状态信息。存储控制元件将同步状态信息发送到所有其他处理器。判断单元基于同步组合信息和所发送的状态信息来判断处理器组是否同步。当处理器组被判断为同步时，处理移位元件移动到组中的所有处理器到程序的下一个处理。

9. 发明授权

US5623688A Parallel processing system including instruction processor to execute instructions and transfer processor to transfer data for each user program 失效
标题翻译：并行处理系统包括指令处理器，用于执行指令并传送处理器以传送每个用户程序的数据
公开(公告)号：US5623688A
公开(公告)日：1997-04-22
申请号：US520231
申请日：1995-08-28
申请人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
发明人： Masayuki Ikeda , Shigeru Nagasawa , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Haruhiko Ueno , Kazushige Kobayakawa , Kenichi Ishizaka
IPC分类号： G06F12/00 , G06F15/17 , G06F15/173 , G06F15/00
CPC分类号： G06F15/17375 , G06F15/17
摘要： A parallel processing system including a plurality of processing units each having a main storage storing instructions and data, an instruction processor reading the instructions from the main storage and executing the instructions, and a transfer processor for making a data transfer in units of a packet which is made up of a header and body data. The parallel processing system further includes a network coupling two processing units which are to make the data transfer based on information included in the header of the packet, where the header includes information related to at least a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor carries out a parallel process for each user process by making a data transfer between the main storage and the network in units of the packet depending on the attribute of the memory access. The transfer processor of at least an arbitrary one of the processing units includes a managing part for managing for each user process a transfer queue base address indicating a first address of a transfer queue in the main storage, a transfer queue write pointer indicating to which data transfer request of the transfer queue the instruction process has enqueued, a transfer queue read pointer indicating to which data transfer request of the transfer queue the transfer processor has finished the data transfer process, and a memory access virtual space.
摘要翻译：一种并行处理系统，包括多个处理单元，每个处理单元具有存储指令和数据的主存储器，从主存储器读取指令并执行指令的指令处理器，以及用于以数据包为单位进行数据传输的传送处理器由头和身体数据组成。该并行处理系统还包括耦合两个处理单元的网络，这两个处理单元是基于包括在分组报头中的信息进行数据传输，其中报头包括与数据的至少目的地有关的信息，存储器的属性访问主存储和一段长度的数据。转移处理器通过根据存储器访问的属性以分组为单位在主存储器和网络之间进行数据传送，为每个用户进程执行并行处理。至少任意一个处理单元的传送处理器包括管理部分，用于为每个用户处理管理指示主存储器中的传送队列的第一地址的传送队列基地址，指示哪个数据转移队列读取指针，指示传输处理器完成数据传输处理的传输队列的哪个数据传输请求以及存储器访问虚拟空间。

10. 发明授权

US5557744A Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors 失效
标题翻译：包括传送队列的多处理器系统和用于控制多个处理器之间的数据传送的中断处理单元
公开(公告)号：US5557744A
公开(公告)日：1996-09-17
申请号：US104482
申请日：1993-07-28
申请人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
发明人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
IPC分类号： G06F15/16 , G06F9/54 , G06F13/24 , G06F15/17 , G06F15/177 , G06F13/00
CPC分类号： G06F15/17 , G06F13/24
摘要： A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfer request, and outputs an enqueuing request to the enqueuing unit to realize the interrupt request.
摘要翻译：多处理器系统具有通过网络彼此并行连接的多个处理器，用于执行相互通信。每个处理器包括用于存储传送请求的传送队列单元，主存储器，用于从另一个处理器接收传送请求的接收单元，以及当传送请求在传送队列单元中排队时将指定数据发送到另一个处理器的传输单元。每个处理器还包括第一寄存器，用于存储指示传输队列单元是否已满的信息，即具有可用于存储传送请求的区域;以及第二寄存器，用于在接收操作期间指示传输请求是否为有效传送请求。保存单元连接到接收单元以暂时保存传送请求，并且提供了一个进入单元，用于将从保存单元传送请求排队到传送队列单元。中断处理单元从接收单元接收中断请求，监视传送队列单元的空/满状态，即监视传输队列单元是否具有可用于存储传送请求的区域，并且向入队队列输出入队请求单元实现中断请求。

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