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1. 发明授权

US4404552A Display device for both a character display and a graphic display 失效
标题翻译：用于字符显示和图形显示的显示设备
公开(公告)号：US4404552A
公开(公告)日：1983-09-13
申请号：US220142
申请日：1980-12-23
申请人： Shigeru Hirahata , Tetsuya Ikeda , Tsuguji Tachiuchi , Shigeru Komatsu , Teruhiro Takezawa
发明人： Shigeru Hirahata , Tetsuya Ikeda , Tsuguji Tachiuchi , Shigeru Komatsu , Teruhiro Takezawa
IPC分类号： G06F17/21 , G09G5/36 , G09G5/40 , G09G1/16
CPC分类号： G09G5/40
摘要： In a display signal generating means in a display device for both the character display and the graphic display, address conversion means is provided for converting the addresses of one character in a plurality of lines of one character section of a memory field corresponding to a display panel into a predetermined address or addresses.
摘要翻译：在用于字符显示和图形显示的显示装置中的显示信号发生装置中，提供地址转换装置，用于转换对应于显示面板的存储器字段的一个字符部分的多个行中的一个字符的地址进入预定的地址或地址。

2. 发明授权

US4388621A Drive circuit for character and graphic display device 失效
标题翻译：字符和图形显示装置的驱动电路
公开(公告)号：US4388621A
公开(公告)日：1983-06-14
申请号：US158263
申请日：1980-06-10
申请人： Shigeru Komatsu , Shigeru Hirahata , Tsuguji Tachiuchi
发明人： Shigeru Komatsu , Shigeru Hirahata , Tsuguji Tachiuchi
IPC分类号： G09G5/24 , G06F3/153 , G09G1/16 , G09G5/00 , G09G5/397 , G09G5/399 , G09G1/00
CPC分类号： G09G5/001
摘要： In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.
摘要翻译：在phi 2循环盗取模式中，选择时钟信号，使得连接到用于显示的定时信号发生器的RAM的时间段被延长，并且相应地缩短RAM连接到CPU的时间段，而不改变整个时期。该时钟信号用于激活用于RAM的开关电路，而具有未修改占空比的时钟信号被施加到CPU，ROM和外部电路，使得来自RAM的显示数据读出周期不会影响CPU时钟频率和其他电路的操作。在该读出期间，多个显示地址信号从定时信号发生器施加到RAM，并且从RAM导出的多个数据顺序地加载到寄存器中，然后在期望的定时读出寄存器，以使得能够显示一个CPU时钟周期内的多个字符。

3. 发明授权

US4417318A Arrangement for control of the operation of a random access memory in a data processing system 失效
标题翻译：用于控制数据处理系统中的随机存取存储器的操作的布置
公开(公告)号：US4417318A
公开(公告)日：1983-11-22
申请号：US35237
申请日：1979-05-02
申请人： Shigeru Hirahata , Teruhiro Takezawa , Nobuo Onuki , Shigeru Komatsu , Tsuguji Tachiuchi
发明人： Shigeru Hirahata , Teruhiro Takezawa , Nobuo Onuki , Shigeru Komatsu , Tsuguji Tachiuchi
IPC分类号： G09G5/00 , G09G1/16 , G09G5/22 , G06F3/00 , G11C11/34
CPC分类号： G09G5/001
摘要： A data processing system has a dynamic type memory, a static type memory for storing data periodically read out, a central processing unit for transferring data to and from the two memories, an address generating circuit for periodically applying an address to the static type memory to read out the contents thereof, and an address selecting unit for exclusively selecting an address from the central processing unit or an address from the address generating circuit. In the system, the two memories are connected to the address selecting unit in order that the address selected by the address selecting means is supplied common to both the memories.
摘要翻译：数据处理系统具有动态型存储器，用于存储周期性读出的数据的静态存储器，用于向两个存储器传送数据的中央处理单元，用于周期性地向静态存储器施加地址的地址生成电路读取其内容，以及地址选择单元，用于从中央处理单元专门选择地址或地址生成电路的地址。在该系统中，两个存储器连接到地址选择单元，以便将由地址选择装置选择的地址提供给两个存储器。

4. 发明授权

US4408197A Pattern display apparatus 失效
标题翻译：图案显示装置
公开(公告)号：US4408197A
公开(公告)日：1983-10-04
申请号：US259162
申请日：1981-04-30
申请人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Shigeru Hirahata
发明人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Shigeru Hirahata
IPC分类号： G06F3/153 , G09G5/22 , G09G5/26 , G09G1/16
CPC分类号： G09G5/227
摘要： A display apparatus for use with a cathode-ray tube capable of displaying patterns in interlaced scanning and non-interlaced scanning operation modes, comprising a composite video signal synthesizer, a memory for storing pattern data, a mode setting circuit for the memory, a data selection signal generator and a raster line number signal generator. The memory stores data for relatively simple patterns such as alphabetical letters and those for relatively complicated patterns such as Chinese characters in individually particular areas in the memory addresses of these different areas are identified by a combination of the data selection signal and the raster line number signal supplied to the memory from the data selection signal generator and the raster line number signal generator. Accordingly, the apparatus is capable of displaying both relatively simple and relatively complicated patterns with satisfactory resolution and with a relatively small-scale structure.
摘要翻译：一种用于能够以隔行扫描和非隔行扫描操作模式显示图案的阴极射线管的显示装置，包括复合视频信号合成器，用于存储图案数据的存储器，用于存储器的模式设置电路，数据选择信号发生器和光栅线数信号发生器。存储器存储用于诸如字母字母的相对简单模式的数据，以及用于相对复杂图案的数据，例如在这些不同区域的存储器地址中的单独特定区域中的汉字，数据选择信号和光栅行号信号从数据选择信号发生器和光栅线数信号发生器提供给存储器。因此，该装置能够以令人满意的分辨率和相对较小规模的结构显示相对简单且相对复杂的图案。

5. 发明授权

US4473879A Data transfer system in which time for transfer of data to a memory is matched to time required to store data in memory 失效
标题翻译：数据传输系统，其中将数据传送到存储器的时间与将数据存储在存储器中所需的时间相匹配
公开(公告)号：US4473879A
公开(公告)日：1984-09-25
申请号：US339654
申请日：1982-01-15
申请人： Tsuguji Tachiuchi , Shigeru Hirahata
发明人： Tsuguji Tachiuchi , Shigeru Hirahata
IPC分类号： H03M9/00 , G06F3/06 , G06F13/00 , G06F13/28 , G06F13/42 , G06F3/00
CPC分类号： G06F13/423 , G06F13/28
摘要： A data transfer system comprises data retaining means for retaining n-bit digital data (n being an integer), serial/parallel data converting means for converting the n-bit digital data transferred from the data retaining means from parallel data to serial data or vice versa in synchronism with first clock signals generated at a first clock frequency, counting means for counting second clock signals generated at a second clock frequency, and control means for transferring the n-bit digital data from the data retaining means to the serial/parallel data converting means each time the counting means counts a predetermined number of clock signals.
摘要翻译：数据传输系统包括用于保持n位数字数据（n为整数）的数据保持装置，串行/并行数据转换装置，用于将从数据保持装置传送的n位数字数据从并行数据转换为串行数据或副与第一时钟频率产生的第一时钟信号同步的计数装置，用于计数以第二时钟频率产生的第二时钟信号的计数装置，以及用于将n位数字数据从数据保持装置传送到串行/并行数据的控制装置每当计数装置计数预定数量的时钟信号时，转换装置。

6. 发明授权

US4298931A Character pattern display system 失效
标题翻译：字符图案显示系统
公开(公告)号：US4298931A
公开(公告)日：1981-11-03
申请号：US44379
申请日：1979-06-01
申请人： Tsuguji Tachiuchi , Shigeru Hirahata , Teruhiro Takezawa
发明人： Tsuguji Tachiuchi , Shigeru Hirahata , Teruhiro Takezawa
IPC分类号： G06F13/18 , G09G1/16 , G09G5/00 , G09G5/22 , G06F13/00
CPC分类号： G09G5/222 , G06F13/18 , G09G5/001
摘要： A data processing system such as a character display system is provided with a first memory circuit for storing coded characters to be displayed, a second memory circuit for storing picture element information of characters to be displayed, and a character display drive circuit for extracting the coded character information from said first memory circuit and extracting and reproducing the picture element information from said second memory circuit. The first memory circuit includes a plurality of random access memories (RAMs). The character display system further includes an address switching circuit for successively and alternately applying an address signal from the character display drive circuit to the RAMs, and an output signal switching circuit for switching the information output signals extracted from the RAMs in synchronism with the switching operation of the address switching circuit. With a simple and relatively inexpensive circuit construction, the character display system may always display characters. The system further includes a clock signal changing means to freely make access to the RAMs without using a program.
摘要翻译：诸如字符显示系统的数据处理系统设置有用于存储要显示的编码字符的第一存储器电路，用于存储要显示的字符的图像元素信息的第二存储器电路，以及用于提取编码的字符显示驱动电路来自所述第一存储器电路的字符信息，并从所述第二存储器电路提取和再现所述图像元素信息。第一存储器电路包括多个随机存取存储器（RAM）。字符显示系统还包括一个地址切换电路，用于将字符显示驱动电路的地址信号连续地交替地施加到RAM;以及输出信号切换电路，用于与切换操作同步地切换从RAM提取的信息输出信号的地址切换电路。通过简单且相对便宜的电路结构，字符显示系统可以总是显示字符。该系统还包括时钟信号改变装置，用于在不使用程序的情况下自由地访问RAM。

7. 发明授权

US4368461A Digital data processing device 失效
标题翻译：数字数据处理装置
公开(公告)号：US4368461A
公开(公告)日：1983-01-11
申请号：US212232
申请日：1980-12-02
申请人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Mikiaki Kobayashi , Toshiyuki Kurita
发明人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Mikiaki Kobayashi , Toshiyuki Kurita
IPC分类号： G09G5/36 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/34 , G09G1/02
CPC分类号： G09G5/001 , G09G5/02
摘要： A digital data processing device in which a color memory has a temporal data storage register at input/output interface thereof so that the data write-in or data read-out operations executed by a micro-processing unit (MPU) is always performed through the temporal storage register. When data read-out or write-in operation is made to a character memory at a certain address, the same operation is simultaneously carried out for the color memory at the corresponding address. Assuming that MPU reads out a certain display address of a display screen, a corresponding character code is fetched by MPU from the character memory, while the corresponding color code is transferred to the temporal storage register from the color memory. When MPU performs the write-in operation for another address of the display screen, the character code held by MPU until then is written in the character memory at a designated address, while the color data i.e. the contents currently held by the temporal storage register are written in the color memory at the address which corresponds to the designated address of the character memory. In this manner, the color data is simultaneously transferred through the software-based processing for transferring only the character code in appearance, whereby the transfer of the contents to be displayed on the display screen can be carried out with an enhanced efficiency.
摘要翻译：一种数字数据处理装置，其中色彩存储器在其输入/输出接口处具有时间数据存储寄存器，使得由微处理单元（MPU）执行的数据写入或数据读出操作总是通过临时存储寄存器。当对特定地址的字符存储器进行数据读出或写入操作时，对于相应地址的彩色存储器同时进行相同的操作。假设MPU读出显示屏幕的某个显示地址，则由MPU从字符存储器取出相应的字符代码，同时将相应的颜色代码从颜色存储器传送到临时存储寄存器。当MPU对显示画面的另一个地址执行写入操作时，由MPU保持的字符代码以指定地址写入字符存储器，而颜色数据即时间存储寄存器当前保持的内容是在对应于字符存储器的指定地址的地址处写入彩色存储器。以这种方式，通过基于软件的处理来同时传送彩色数据，用于仅传送字符代码的外观，从而能够以提高的效率进行显示在显示画面上的内容的传送。

8. 发明授权

US4388707A Memory selecting system 失效
标题翻译：内存选择系统
公开(公告)号：US4388707A
公开(公告)日：1983-06-14
申请号：US279071
申请日：1981-06-30
申请人： Shigeru Komatsu , Kazushi Mizukami , Tsuguji Tachiuchi , Kunihiko Nagai , Takuo Koyama
发明人： Shigeru Komatsu , Kazushi Mizukami , Tsuguji Tachiuchi , Kunihiko Nagai , Takuo Koyama
IPC分类号： G06F12/00 , G06F12/06 , G11C8/12 , G11C8/00
CPC分类号： G11C8/12 , G06F12/0623
摘要： A memory selection system which facilitates the addition of an external memory to a digital processing unit having an internal memory is disclosed. When a plurality of memories have the same addresses and an overlapped address is accessed, priority among the memories having the overlapped address is discriminated to enable only the memory having the highest priority (last attached memory) to be selected for access and to disable the access of the other memories.
摘要翻译：公开了一种便于将外部存储器添加到具有内部存储器的数字处理单元的存储器选择系统。当多个存储器具有相同的地址并且重叠地址被访问时，区分具有重叠地址的存储器中的优先级，以使得仅能够选择具有最高优先级的存储器（最后附加存储器）以进行访问并禁用访问的其他记忆。

9. 发明授权

US4839739A Image signal binary circuit with a variable-frequency clock signal generator for driving an image sensor 失效
标题翻译：具有用于驱动图像传感器的可变频率时钟信号发生器的图像信号二进制电路
公开(公告)号：US4839739A
公开(公告)日：1989-06-13
申请号：US23262
申请日：1987-03-09
申请人： Tsuguji Tachiuchi , Satoshi Konuma , Nobuo Tsuchiya
发明人： Tsuguji Tachiuchi , Satoshi Konuma , Nobuo Tsuchiya
IPC分类号： H04N1/40 , H04N1/403
CPC分类号： H04N1/403 , H04N1/40056
摘要： A one-dimensional image sensor comprising a solid image pick-up element takes images in sequence, and generates an image signal. Clock pulses from a frequency variable type clock pulse generator having a frequency which varies in correspondence to a control signal are supplied to a one-dimensional image sensor, thereby image signals are outputted in sequence. The image signal is amplified by an amplifier and inputted to a comparator and compared with a reference signal. A frequency variable range of the frequency variable type clock pulse generator is set higher than the cut-off frequency of the amplifier, and the binary level output by the comparator is substantially the same as the image inputted to the one-dimensional image sensor and control is effected by the variable frequency of the clock pulses.
摘要翻译：包括实心图像拾取元件的一维图像传感器依次拍摄图像并产生图像信号。来自具有对应于控制信号变化的频率的频率可变型时钟脉冲发生器的时钟脉冲被提供给一维图像传感器，由此依次输出图像信号。图像信号被放大器放大并输入到比较器并与参考信号进行比较。频率可变型时钟脉冲发生器的频率可变范围被设置为高于放大器的截止频率，并且由比较器输出的二进制电平基本上与输入到一维图像传感器的图像和控制受时钟脉冲的可变频率的影响。

10. 发明授权

US4808991A Method and apparatus for liquid crystal display with intermediate tone 失效
标题翻译：具有中间色调的液晶显示方法和装置
公开(公告)号：US4808991A
公开(公告)日：1989-02-28
申请号：US2198
申请日：1987-01-12
申请人： Tsuguji Tachiuchi , Hiroyuki Mano , Terumi Takashi
发明人： Tsuguji Tachiuchi , Hiroyuki Mano , Terumi Takashi
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3611 , G09G3/2018
摘要： A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.
摘要翻译：液晶显示器能够显示中间，部分或半色调的图像，同时防止发生闪烁和液晶面板的衰减。要以中间色调显示的数据的显示操作具有在每个帧期间被禁止显示的显示数据的重复帧的一行或多行。这种被禁止的显示行在连续的帧上以顺序的方式被指定为不同，并且指定序列根据改变的模式在连续的帧中变化。

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