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1. 发明授权

US4388621A Drive circuit for character and graphic display device 失效
标题翻译：字符和图形显示装置的驱动电路
公开(公告)号：US4388621A
公开(公告)日：1983-06-14
申请号：US158263
申请日：1980-06-10
申请人： Shigeru Komatsu , Shigeru Hirahata , Tsuguji Tachiuchi
发明人： Shigeru Komatsu , Shigeru Hirahata , Tsuguji Tachiuchi
IPC分类号： G09G5/24 , G06F3/153 , G09G1/16 , G09G5/00 , G09G5/397 , G09G5/399 , G09G1/00
CPC分类号： G09G5/001
摘要： In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.
摘要翻译：在phi 2循环盗取模式中，选择时钟信号，使得连接到用于显示的定时信号发生器的RAM的时间段被延长，并且相应地缩短RAM连接到CPU的时间段，而不改变整个时期。该时钟信号用于激活用于RAM的开关电路，而具有未修改占空比的时钟信号被施加到CPU，ROM和外部电路，使得来自RAM的显示数据读出周期不会影响CPU时钟频率和其他电路的操作。在该读出期间，多个显示地址信号从定时信号发生器施加到RAM，并且从RAM导出的多个数据顺序地加载到寄存器中，然后在期望的定时读出寄存器，以使得能够显示一个CPU时钟周期内的多个字符。

2. 发明授权

US4404552A Display device for both a character display and a graphic display 失效
标题翻译：用于字符显示和图形显示的显示设备
公开(公告)号：US4404552A
公开(公告)日：1983-09-13
申请号：US220142
申请日：1980-12-23
申请人： Shigeru Hirahata , Tetsuya Ikeda , Tsuguji Tachiuchi , Shigeru Komatsu , Teruhiro Takezawa
发明人： Shigeru Hirahata , Tetsuya Ikeda , Tsuguji Tachiuchi , Shigeru Komatsu , Teruhiro Takezawa
IPC分类号： G06F17/21 , G09G5/36 , G09G5/40 , G09G1/16
CPC分类号： G09G5/40
摘要： In a display signal generating means in a display device for both the character display and the graphic display, address conversion means is provided for converting the addresses of one character in a plurality of lines of one character section of a memory field corresponding to a display panel into a predetermined address or addresses.
摘要翻译：在用于字符显示和图形显示的显示装置中的显示信号发生装置中，提供地址转换装置，用于转换对应于显示面板的存储器字段的一个字符部分的多个行中的一个字符的地址进入预定的地址或地址。

3. 发明授权

US4417318A Arrangement for control of the operation of a random access memory in a data processing system 失效
标题翻译：用于控制数据处理系统中的随机存取存储器的操作的布置
公开(公告)号：US4417318A
公开(公告)日：1983-11-22
申请号：US35237
申请日：1979-05-02
申请人： Shigeru Hirahata , Teruhiro Takezawa , Nobuo Onuki , Shigeru Komatsu , Tsuguji Tachiuchi
发明人： Shigeru Hirahata , Teruhiro Takezawa , Nobuo Onuki , Shigeru Komatsu , Tsuguji Tachiuchi
IPC分类号： G09G5/00 , G09G1/16 , G09G5/22 , G06F3/00 , G11C11/34
CPC分类号： G09G5/001
摘要： A data processing system has a dynamic type memory, a static type memory for storing data periodically read out, a central processing unit for transferring data to and from the two memories, an address generating circuit for periodically applying an address to the static type memory to read out the contents thereof, and an address selecting unit for exclusively selecting an address from the central processing unit or an address from the address generating circuit. In the system, the two memories are connected to the address selecting unit in order that the address selected by the address selecting means is supplied common to both the memories.
摘要翻译：数据处理系统具有动态型存储器，用于存储周期性读出的数据的静态存储器，用于向两个存储器传送数据的中央处理单元，用于周期性地向静态存储器施加地址的地址生成电路读取其内容，以及地址选择单元，用于从中央处理单元专门选择地址或地址生成电路的地址。在该系统中，两个存储器连接到地址选择单元，以便将由地址选择装置选择的地址提供给两个存储器。

4. 发明授权

US4408197A Pattern display apparatus 失效
标题翻译：图案显示装置
公开(公告)号：US4408197A
公开(公告)日：1983-10-04
申请号：US259162
申请日：1981-04-30
申请人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Shigeru Hirahata
发明人： Shigeru Komatsu , Kunihiko Nagai , Takuo Koyama , Tsuguji Tachiuchi , Shigeru Hirahata
IPC分类号： G06F3/153 , G09G5/22 , G09G5/26 , G09G1/16
CPC分类号： G09G5/227
摘要： A display apparatus for use with a cathode-ray tube capable of displaying patterns in interlaced scanning and non-interlaced scanning operation modes, comprising a composite video signal synthesizer, a memory for storing pattern data, a mode setting circuit for the memory, a data selection signal generator and a raster line number signal generator. The memory stores data for relatively simple patterns such as alphabetical letters and those for relatively complicated patterns such as Chinese characters in individually particular areas in the memory addresses of these different areas are identified by a combination of the data selection signal and the raster line number signal supplied to the memory from the data selection signal generator and the raster line number signal generator. Accordingly, the apparatus is capable of displaying both relatively simple and relatively complicated patterns with satisfactory resolution and with a relatively small-scale structure.
摘要翻译：一种用于能够以隔行扫描和非隔行扫描操作模式显示图案的阴极射线管的显示装置，包括复合视频信号合成器，用于存储图案数据的存储器，用于存储器的模式设置电路，数据选择信号发生器和光栅线数信号发生器。存储器存储用于诸如字母字母的相对简单模式的数据，以及用于相对复杂图案的数据，例如在这些不同区域的存储器地址中的单独特定区域中的汉字，数据选择信号和光栅行号信号从数据选择信号发生器和光栅线数信号发生器提供给存储器。因此，该装置能够以令人满意的分辨率和相对较小规模的结构显示相对简单且相对复杂的图案。

5. 发明授权

US4473879A Data transfer system in which time for transfer of data to a memory is matched to time required to store data in memory 失效
标题翻译：数据传输系统，其中将数据传送到存储器的时间与将数据存储在存储器中所需的时间相匹配
公开(公告)号：US4473879A
公开(公告)日：1984-09-25
申请号：US339654
申请日：1982-01-15
申请人： Tsuguji Tachiuchi , Shigeru Hirahata
发明人： Tsuguji Tachiuchi , Shigeru Hirahata
IPC分类号： H03M9/00 , G06F3/06 , G06F13/00 , G06F13/28 , G06F13/42 , G06F3/00
CPC分类号： G06F13/423 , G06F13/28
摘要： A data transfer system comprises data retaining means for retaining n-bit digital data (n being an integer), serial/parallel data converting means for converting the n-bit digital data transferred from the data retaining means from parallel data to serial data or vice versa in synchronism with first clock signals generated at a first clock frequency, counting means for counting second clock signals generated at a second clock frequency, and control means for transferring the n-bit digital data from the data retaining means to the serial/parallel data converting means each time the counting means counts a predetermined number of clock signals.
摘要翻译：数据传输系统包括用于保持n位数字数据（n为整数）的数据保持装置，串行/并行数据转换装置，用于将从数据保持装置传送的n位数字数据从并行数据转换为串行数据或副与第一时钟频率产生的第一时钟信号同步的计数装置，用于计数以第二时钟频率产生的第二时钟信号的计数装置，以及用于将n位数字数据从数据保持装置传送到串行/并行数据的控制装置每当计数装置计数预定数量的时钟信号时，转换装置。

6. 发明授权

US4298931A Character pattern display system 失效
标题翻译：字符图案显示系统
公开(公告)号：US4298931A
公开(公告)日：1981-11-03
申请号：US44379
申请日：1979-06-01
申请人： Tsuguji Tachiuchi , Shigeru Hirahata , Teruhiro Takezawa
发明人： Tsuguji Tachiuchi , Shigeru Hirahata , Teruhiro Takezawa
IPC分类号： G06F13/18 , G09G1/16 , G09G5/00 , G09G5/22 , G06F13/00
CPC分类号： G09G5/222 , G06F13/18 , G09G5/001
摘要： A data processing system such as a character display system is provided with a first memory circuit for storing coded characters to be displayed, a second memory circuit for storing picture element information of characters to be displayed, and a character display drive circuit for extracting the coded character information from said first memory circuit and extracting and reproducing the picture element information from said second memory circuit. The first memory circuit includes a plurality of random access memories (RAMs). The character display system further includes an address switching circuit for successively and alternately applying an address signal from the character display drive circuit to the RAMs, and an output signal switching circuit for switching the information output signals extracted from the RAMs in synchronism with the switching operation of the address switching circuit. With a simple and relatively inexpensive circuit construction, the character display system may always display characters. The system further includes a clock signal changing means to freely make access to the RAMs without using a program.
摘要翻译：诸如字符显示系统的数据处理系统设置有用于存储要显示的编码字符的第一存储器电路，用于存储要显示的字符的图像元素信息的第二存储器电路，以及用于提取编码的字符显示驱动电路来自所述第一存储器电路的字符信息，并从所述第二存储器电路提取和再现所述图像元素信息。第一存储器电路包括多个随机存取存储器（RAM）。字符显示系统还包括一个地址切换电路，用于将字符显示驱动电路的地址信号连续地交替地施加到RAM;以及输出信号切换电路，用于与切换操作同步地切换从RAM提取的信息输出信号的地址切换电路。通过简单且相对便宜的电路结构，字符显示系统可以总是显示字符。该系统还包括时钟信号改变装置，用于在不使用程序的情况下自由地访问RAM。

7. 发明授权

US4591845A Character and graphic signal generating apparatus 失效
标题翻译：字符和图形信号发生装置
公开(公告)号：US4591845A
公开(公告)日：1986-05-27
申请号：US534684
申请日：1983-09-22
申请人： Shigeru Komatsu , Shigeru Hirahata
发明人： Shigeru Komatsu , Shigeru Hirahata
IPC分类号： G06F3/153 , G09G5/40 , G09G1/16
CPC分类号： G09G5/40
摘要： A character and graphic signal generating apparatus of the type suitable for use with a personal computer for displaying characters and graphic patterns in a superposed relation according to a raster scan method comprises a frame buffer for storing coded character data, a DMA control unit for controlling DMA transfer of coded character data from a display RAM to the frame buffer in a non-display cycle, and units for reading out the data from the display RAM and the frame buffer in parallel relation in a display cycle so as to simultaneously derive the graphic data and the coded character data in each display cycle, whereby more display data can be read out in a unit time, and high-density display can be achieved without the sacrifice of the scanning speed.
摘要翻译：根据光栅扫描方法，适用于以个人计算机用于显示字符和叠加关系的图形的字符和图形信号发生装置包括用于存储编码字符数据的帧缓冲器，用于控制DMA的DMA控制单元在非显示周期中将编码字符数据从显示RAM传送到帧缓冲器，以及用于在显示周期中并行地从显示RAM和帧缓冲器读出数据的单元，以便同时导出图形数据和每个显示周期中的编码字符数据，从而可以在单位时间内读出更多的显示数据，并且可以在不牺牲扫描速度的情况下实现高密度显示。

8. 发明授权

US06898578B2 Recording apparatus for recording digital information 失效
公开(公告)号：US06898578B2
公开(公告)日：2005-05-24
申请号：US10210107
申请日：2002-08-02
申请人： Manabu Sasamoto , Takaharu Noguchi , Makoto Aikawa , Shigeru Hirahata
发明人： Manabu Sasamoto , Takaharu Noguchi , Makoto Aikawa , Shigeru Hirahata
IPC分类号： H04N5/91 , G06F21/10 , G09C1/00 , G11B20/00 , G11B20/10 , H04N5/913 , H04N7/167 , H04N9/804 , H04N21/41 , H04N21/8355 , H04L9/00 , G06F17/60 , H04K1/00
CPC分类号： H04N21/4135 , G11B20/00086 , G11B20/0021 , G11B20/00507 , G11B20/00753 , G11B20/00768 , G11B20/0084 , H04N5/913 , H04N7/1675 , H04N9/804 , H04N9/8042 , H04N21/8355 , H04N2005/91328 , H04N2005/91364
摘要： A digital information recording apparatus to record digital information to protect copyright of digital information that includes at least first digital information and first copy control information. The digital information recording apparatus records the digital information based upon the first copy control information, which denotes one of: a copy inhibition prohibiting copying of said first digital information; a limited copy permission authorizing a predetermined number of times of copying of said first digital information; and an unlimited copy permission authorizing unlimited copying of said first digital information.

9. 发明授权

US4733300A Contour signal correction circuit for television receiver 失效
标题翻译：电视接收机轮廓信号校正电路
公开(公告)号：US4733300A
公开(公告)日：1988-03-22
申请号：US938962
申请日：1986-12-08
申请人： Masato Sugiyama , Isao Nakagawa , Shigeru Hirahata , Kenji Katsumata , Sunao Suzuki
发明人： Masato Sugiyama , Isao Nakagawa , Shigeru Hirahata , Kenji Katsumata , Sunao Suzuki
IPC分类号： H04N5/21 , H04N5/14 , H04N5/208 , H04N5/28 , H04N7/01 , H04N5/44
CPC分类号： H04N5/142 , H04N7/012
摘要： In combination, a signal processing circuit for television signals includes a contour signal correction circuit for use in a television receiver and a scanning line interpolation circuit for converting a television signal of a signal structure for interlaced scanning into a television signal for sequential scanning.
摘要翻译：综合起来，用于电视信号的信号处理电路包括用于电视接收机的轮廓信号校正电路和用于将用于隔行扫描的信号结构的电视信号转换成用于顺序扫描的电视信号的扫描线内插电路。

10. 发明授权

US4733297A Video signal processing circuit of motion adaptive type 失效
标题翻译：运动自适应型视频信号处理电路
公开(公告)号：US4733297A
公开(公告)日：1988-03-22
申请号：US36431
申请日：1987-04-09
申请人： Kenji Katsumata , Masato Sugiyama , Akihide Okuda , Shigeru Hirahata , Isao Nakagawa , Sunao Suzuki
发明人： Kenji Katsumata , Masato Sugiyama , Akihide Okuda , Shigeru Hirahata , Isao Nakagawa , Sunao Suzuki
IPC分类号： H04N11/20 , H04N5/14 , H04N7/01 , H04N9/78
CPC分类号： H04N5/144 , H04N7/012 , H04N9/78
摘要： A video signal processing circuit of motion adaptive type includes a circuit for identifying motion of a picture in a video signal on the basis of a difference signal between at least a line signal appearing in an M-th field and a corresponding line signal appearing in an (M-1)th field so that, when a scanning line produced on the basis of the video signal is interpolated between scanning lines of the video signal to improve the picture quality, a signal for interpolating said scanning line is produced in a different manner depending on whether a portion of the video signal to the displayed is a still picture or a moving picture. The motion identifying circuit comprises a horizontal filter spreading the difference signal in the horizontal direction, a circuit delaying the output signal of the horizontal filter by one field after attenuation, a line memory delaying the output signal of the attenuating and delaying circuit by one line, and an output circuit generating a signal identifying the motion of the picture on the basis of the output signals of the horizontal filter, attenuating and delaying circuit and line memory.
摘要翻译：运动自适应型视频信号处理电路包括一个电路，用于根据出现在第M场的线路信号和出现在第M场的相应线路信号之间的差分信号识别视频信号中的图像的运动（M-1）场，使得当基于视频信号产生的扫描线被内插在视频信号的扫描线之间以提高图像质量时，以不同的方式产生用于内插所述扫描线的信号取决于所显示的视频信号的一部分是静止图像还是运动图像。运动识别电路包括在水平方向上扩展差分信号的水平滤波器，将衰减后的水平滤波器的输出信号延迟一个场的电路，将存储器的衰减延迟电路的输出信号延迟一行，以及输出电路，其基于水平滤波器的输出信号，衰减和延迟电路和行存储器来产生识别图像的运动的信号。

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