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1. 发明授权

US06426915B2 Fast cycle RAM and data readout method therefor 失效
标题翻译：快速循环RAM及其数据读出方法
公开(公告)号：US06426915B2
公开(公告)日：2002-07-30
申请号：US09749008
申请日：2000-12-27
申请人： Shigeo Ohshima , Nobuo Watanabe
发明人： Shigeo Ohshima , Nobuo Watanabe
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/409
摘要： A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.
摘要翻译：行访问命令和列访问命令在两个连续的时钟周期中作为一个分组提供给FCRAM，以便缩短随机访问时间和随机周期时间。此时，通过使用第一命令来进行读/写操作的定义，并且响应于第一命令获取存储单元阵列的解码地址。当响应于第一命令获取存储单元阵列的解码地址时，常规SDR / DDR-SDRAM的命令控制引脚用作地址引脚。

2. 发明授权

US06522600B2 Fast cycle RAM and data readout method therefor 失效
标题翻译：快速循环RAM及其数据读出方法
公开(公告)号：US06522600B2
公开(公告)日：2003-02-18
申请号：US10163797
申请日：2002-06-04
申请人： Shigeo Ohshima , Nobuo Watanabe
发明人： Shigeo Ohshima , Nobuo Watanabe
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/409
摘要： A semiconductor memory device comprises first and second pins, a controller, a first command decoder and a lower-side command decoder. The controller is supplied with a signal indicating that a read command is input and a signal indicating that a write command is input based on the signal input to the first pin. The first command decoder is controlled by an output signal of the controller, defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via the second pin and decodes the first command. A lower-side command decoder is controlled by an output signal of the controller, fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command, and outputs a lower address latch command, mode register set command and auto-refresh command.
摘要翻译：半导体存储器件包括第一和第二引脚，控制器，第一命令解码器和下侧命令解码器。控制器被提供有指示读取命令被输入的信号和表示基于输入到第一引脚的信号来输入写入命令的信号。第一命令解码器由控制器的输出信号控制，通过使用第一命令定义读/写操作，经由第二引脚取出存储单元阵列的上侧解码地址，并解码第一命令。下位命令解码器由控制器的输出信号控制，响应于第二命令经由控制引脚取出存储单元阵列的下侧解码地址，对下侧命令进行解码，并输出低位指令译码器地址锁存命令，模式寄存器设置命令和自动刷新命令。

3. 发明授权

US06757214B2 Synchronous type semiconductor memory device 失效
标题翻译：同步型半导体存储器件
公开(公告)号：US06757214B2
公开(公告)日：2004-06-29
申请号：US10443439
申请日：2003-05-22
申请人： Kazuaki Kawaguchi , Shigeo Ohshima , Nobuo Watanabe , Yoshinori Ogawa
发明人： Kazuaki Kawaguchi , Shigeo Ohshima , Nobuo Watanabe , Yoshinori Ogawa
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1045 , G11C7/1072
摘要： A synchronous type semiconductor device which inputs/outputs data with respect to a host includes a memory circuit, command decoder and CAS latency setting circuit. The command decoder decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit. The command includes a read command and mode register set command. The CAS latency setting circuit sets CAS latency in a read cycle based on a predetermined command output from the command decoder and a function control signal input from the host. The predetermined command is a command other than the mode register set command.
摘要翻译：相对于主机输入/输出数据的同步型半导体器件包括存储器电路，命令解码器和CAS延迟设置电路。命令解码器与从主机输入的时钟同步地解码从主机输入的命令控制信号，并将解码的命令输出到存储器电路。该命令包括读命令和模式寄存器设置命令。 CAS延迟设置电路基于从命令解码器输出的预定命令和从主机输入的功能控制信号在读周期中设置CAS等待时间。预定命令是除模式寄存器设置命令之外的命令。

4. 发明授权

US06867993B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06867993B2
公开(公告)日：2005-03-15
申请号：US09910603
申请日：2001-07-19
申请人： Shigeo Ohshima , Nobuo Watanabe
发明人： Shigeo Ohshima , Nobuo Watanabe
IPC分类号： G11C11/401 , G11C5/06 , G11C29/34
CPC分类号： G11C5/066 , H01L2224/4826
摘要： In the package, a semiconductor chip is accommodated. This semiconductor chip has n pads (n is a natural number). The package has n pins connected to n pads.
摘要翻译：在封装中，容纳半导体芯片。该半导体芯片具有n个焊盘（n是自然数）。该封装有n个引脚连接到n个焊盘。

5. 发明授权

US07986557B2 Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system 有权
标题翻译：非易失性半导体存储器件和非易失性半导体存储器系统
公开(公告)号：US07986557B2
公开(公告)日：2011-07-26
申请号：US12533529
申请日：2009-07-31
申请人： Naoya Tokiwa , Shigeo Ohshima
发明人： Naoya Tokiwa , Shigeo Ohshima
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , G11C8/06 , G11C8/10 , G11C16/0483
摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.
摘要翻译：存储器可以包括字线; 位线对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

6. 发明授权

US06768691B2 Semiconductor integrated circuit and memory system 有权
标题翻译：半导体集成电路和存储器系统
公开(公告)号：US06768691B2
公开(公告)日：2004-07-27
申请号：US10241908
申请日：2002-09-12
申请人： Noriyasu Kumazaki , Keiji Maruyama , Shigeo Ohshima
发明人： Noriyasu Kumazaki , Keiji Maruyama , Shigeo Ohshima
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066
摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.
摘要翻译：一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。

7. 发明授权

US06483772B2 Semiconductor memory device capable of masking data to be written 失效
公开(公告)号：US06483772B2
公开(公告)日：2002-11-19
申请号：US09951230
申请日：2001-09-12
申请人： Susumu Ozawa , Shigeo Ohshima , Katsumi Abe
发明人： Susumu Ozawa , Shigeo Ohshima , Katsumi Abe
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.

8. 发明授权

US06198690B1 Clock control circuit with an input stop circuit 有权
标题翻译：具有输入停止电路的时钟控制电路
公开(公告)号：US06198690B1
公开(公告)日：2001-03-06
申请号：US09503000
申请日：2000-02-14
申请人： Koji Kato , Masahiro Kamoshida , Shigeo Ohshima
发明人： Koji Kato , Masahiro Kamoshida , Shigeo Ohshima
IPC分类号： G11C800
CPC分类号： G11C7/225 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/135
摘要： A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.
摘要翻译：时钟控制电路包括：正向脉冲延迟电路，包括用于延迟正向脉冲信号FCL的多个延迟电路;包括用于延迟反向脉冲信号RCL的多个延迟电路的反向脉冲延迟电路;状态保持部分，包括：多个状态保持电路，用于根据正向脉冲延迟电路中的正向脉冲信号的发送条件控制反向脉冲延迟电路的操作;以及输入停止电路，用于停止输入对应于外部时钟信号的脉冲在从外部时钟信号开始供给的时刻起的规定期间内向后向脉冲延迟电路发送。

9. 发明授权

US6163501A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US6163501A
公开(公告)日：2000-12-19
申请号：US520720
申请日：2000-03-08
申请人： Shigeo Ohshima , Susumu Ozawa
发明人： Shigeo Ohshima , Susumu Ozawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C11/407 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C2207/107
摘要： A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentially transferred to the same peripheral data line as the one of the peripheral data lines, to which the head data have been transferred. Thus, it is possible to decrease the number of peripheral data lines to reduce the chip size of an SDRAM while adopting a pre-fetch system for accelerating a data transfer cycle.
摘要翻译：同步半导体存储器件包括：存储单元阵列; 解码器电路，用于对与时钟同步地提供的地址进行解码，以选择存储单元阵列的存储单元; 传送存储单元阵列的数据的多个主数据线对; 多个数据线缓冲器，每个数据线缓冲器被提供在相应的一个主数据线对中，并且每个数据线缓冲器包括一个锁存电路; 以及用于将每个数据线缓冲器的数据传送到数据输入/输出端子的多个外围数据线，其中从存储单元阵列读出的每个数据输入/输出端子的多个数据位被传送到数据并行地经由主数据线对的行缓冲器，并且当多个数据位的头数据通过锁存电路以传送到外围数据线之一时，多个连续数据被锁存电路暂时保持并且随后的数据被顺序传送到与传送头数据的外围数据线之一相同的外围数据线。因此，可以减少外围数据线的数量，以减少SDRAM的芯片尺寸，同时采用用于加速数据传输周期的预取系统。

10. 发明授权

US5051954A Semiconductor memory device 失效
公开(公告)号：US5051954A
公开(公告)日：1991-09-24
申请号：US406420
申请日：1989-09-11
申请人： Haruki Toda , Shigeo Ohshima , Tatsuo Ikawa
发明人： Haruki Toda , Shigeo Ohshima , Tatsuo Ikawa
IPC分类号： G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/10
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096
摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

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