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1. 发明授权

US06459125B2 SOI based transistor inside an insulation layer with conductive bump on the insulation layer 失效
标题翻译：绝缘层内的SOI基晶体管，绝缘层上有导电凸块
公开(公告)号：US06459125B2
公开(公告)日：2002-10-01
申请号：US09122863
申请日：1998-07-27
申请人： Shigenobu Maeda , Tadashi Nishimura , Kazuhito Tsutsumi , Shigeto Maegawa , Yuuichi Hirano
发明人： Shigenobu Maeda , Tadashi Nishimura , Kazuhito Tsutsumi , Shigeto Maegawa , Yuuichi Hirano
IPC分类号： H01L2900
CPC分类号： H01L23/556 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/12 , H01L29/786 , H01L2224/03914 , H01L2224/0401 , H01L2224/05624 , H01L2224/11334 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/131 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
摘要翻译：提供用于CSP安装的半导体器件，其避免由于α射线引起的误差并且具有高抗应力。在半导体衬底（101）上形成掩埋氧化膜（107），在掩埋氧化膜（107）上形成具有SOI结构的MOS晶体管。 MOS晶体管包括形成在半导体层（120）中的源区和漏区（120a，120b）和栅电极（110）。通过未示出的连接机构连接到源极和漏极区域（120a，120b）中的任何一个的铝焊盘（103）和在铝焊盘（103）的顶部具有开口的氮化硅膜（104）形成在层间绝缘膜（108）上。形成从铝焊盘（103）向氮化硅膜（104）的一端延伸的钛（105）层和镍层（106）。焊料凸块（11）设置在镍层（106）上。

2. 发明申请

US20050167673A1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20050167673A1
公开(公告)日：2005-08-04
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L21/265 , H01L21/336 , H01L27/11 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

3. 发明授权

US07187040B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07187040B2
公开(公告)日：2007-03-06
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

4. 发明授权

US07112854B1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07112854B1
公开(公告)日：2006-09-26
申请号：US08850631
申请日：1997-05-02
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

5. 发明授权

US07321152B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07321152B2
公开(公告)日：2008-01-22
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

6. 发明申请

US20060267012A1 Thin-film transistor and method of fabricating the same 失效
公开(公告)号：US20060267012A1
公开(公告)日：2006-11-30
申请号：US11498800
申请日：2006-08-04
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L31/00
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

7. 发明授权

US06255719B1 Semiconductor device including thermal neutron absorption material 失效
标题翻译：包括热中子吸收材料的半导体器件
公开(公告)号：US06255719B1
公开(公告)日：2001-07-03
申请号：US09201833
申请日：1998-12-01
申请人： Hirotada Kuriyama , Kazuhito Tsutsumi , Yutaka Arita , Tatsuhiko Akiyama , Tadafumi Kishimoto
发明人： Hirotada Kuriyama , Kazuhito Tsutsumi , Yutaka Arita , Tatsuhiko Akiyama , Tadafumi Kishimoto
IPC分类号： H01L23552
CPC分类号： H01L23/556 , H01L23/552 , H01L2924/0002 , H01L2924/1627 , Y10S257/913 , H01L2924/00
摘要： A boron nitride inclusion sheet is applied on the surface of a mold package enclosing a semiconductor chip so as to prevent soft error caused by a thermal neutron.
摘要翻译：在封装半导体芯片的模具封装的表面上施加氮化硼夹层板，以防止由热中子引起的软误差。

8. 发明授权

US6018181A Thin film transistor and manufacturing method thereof 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US6018181A
公开(公告)日：2000-01-25
申请号：US358050
申请日：1994-12-16
申请人： Kazuhito Tsutsumi
发明人： Kazuhito Tsutsumi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01 , H01L27/12
CPC分类号： H01L29/66765 , H01L29/78624 , H01L29/78636
摘要： A thin film transistor has a gate electrode formed of polysilicon on a surface of an insulating substrate or an insulating layer. The surface of the gate electrode is covered with a dielectric layer. A polysilicon layer is formed on a surface of the dielectric layer and source/drain regions are formed in this polysilicon layer. The dielectric layer covers the surface of the gate electrode and has its surface made flat. The source/drain regions are formed in the polysilicon layer on the surface of this flat dielectric layer. In another embodiment, a dielectric layer has a 2-layered structure with sidewall insulating layers located on sidewalls of a gate electrode and another insulating layer covering a surface of the gate electrode and surfaces of the sidewall insulating layers. By having larger film thickness of the dielectric layer in the vicinity of a side portion of the gate electrode than that above the gate electrode, the electric field concentration is modified in the vicinity thereof.
摘要翻译：薄膜晶体管具有在绝缘基板或绝缘层的表面上由多晶硅形成的栅电极。栅电极的表面被电介质层覆盖。在电介质层的表面上形成多晶硅层，在该多晶硅层中形成源/漏区。电介质层覆盖栅电极的表面并使其表面平坦。源极/漏极区域形成在该平坦介电层的表面上的多晶硅层中。在另一个实施例中，介电层具有2层结构，其中侧壁绝缘层位于栅电极的侧壁上，另一绝缘层覆盖栅电极的表面和侧壁绝缘层的表面。通过使栅电极侧部附近的电介质层的膜厚比上述栅极电极的膜厚大，在其附近改变电场浓度。

9. 发明授权

US06501178B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06501178B1
公开(公告)日：2002-12-31
申请号：US08795176
申请日：1997-02-04
申请人： Hirotada Kuriyama , Kazuhito Tsutsumi
发明人： Hirotada Kuriyama , Kazuhito Tsutsumi
IPC分类号： H01L2348
CPC分类号： H01L27/11 , H01L23/5226 , H01L27/1108 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： In a semiconductor device, a first conductive layer (2) is located on a semiconductor substrate (14) through an insulating film (13a) and beneath a first insulating layer (13f). On the first insulating layer (13f) is formed a second conductive layer (8) followed by a second insulating layer (13g), either or both of which are very thin. A third conductive layer (6) is placed on the second insulating layer (13g). A connecting column (16) extends from the third conducting layer (6) through and forming an end contact with the second conductive layer (8) to the first conducting layer (2) and the substrate (14), with a greater portion of the column resting upon the substrate (14). The third conductive layer (6) forms the gate electrode (6b) of a top gate type TFT.
摘要翻译：在半导体器件中，第一导电层（2）通过绝缘膜（13a）位于半导体衬底（14）上并位于第一绝缘层（13f）下方。在第一绝缘层（13f）上形成第二导电层（8），随后是第二绝缘层（13g），其中一个或两者都非常薄。第三导电层（6）放置在第二绝缘层（13g）上。连接柱（16）从第三导电层（6）延伸穿过并与第二导电层（8）形成与第一导电层（2）和基板（14）的端部接触，其中较大部分的柱放置在基底（14）上。第三导电层（6）形成顶栅型TFT的栅电极（6b）。

10. 发明授权

US06169313A Static semiconductor memory device 有权
标题翻译：静态半导体存储器件
公开(公告)号：US06169313A
公开(公告)日：2001-01-02
申请号：US09328588
申请日：1999-06-10
申请人： Kazuhito Tsutsumi , Motoi Ashida , Yoshiyuki Haraguti , Hideaki Nagaoka , Eiji Hamasuna , Yoshikazu Kamitani
发明人： Kazuhito Tsutsumi , Motoi Ashida , Yoshiyuki Haraguti , Hideaki Nagaoka , Eiji Hamasuna , Yoshikazu Kamitani
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/904
摘要： A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.
摘要翻译：在两个负载晶体管中的每一个的漏极有源区域的侧面上设置共用触点。因此，在具有共享接点的全CMOS型SRAM存储单元中确保了稳定的低电压操作。

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