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1. 发明授权

US5536665A Method of manufacturing a semiconductor device with double structured well 失效
标题翻译：制造具有双重结构井的半导体器件的方法
公开(公告)号：US5536665A
公开(公告)日：1996-07-16
申请号：US442928
申请日：1995-05-17
申请人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
发明人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L21/266
CPC分类号： H01L27/0921 , H01L27/10805 , Y10S148/085
摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.
摘要翻译：半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱。在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

2. 发明授权

US5446305A Semiconductor device with double structured well 失效
标题翻译：具有双重结构井的半导体器件
公开(公告)号：US5446305A
公开(公告)日：1995-08-29
申请号：US240282
申请日：1994-05-09
申请人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
发明人： Shigeki Komori , Takashi Kuroi , Masahide Inuishi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L27/02 , H01L29/70
CPC分类号： H01L27/0921 , H01L27/10805 , Y10S148/085
摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.
摘要翻译：半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱。在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

3. 发明授权

US06420763B1 Semiconductor device having a retrograde well structure and method of manufacturing thereof 失效
标题翻译：具有逆行井结构的半导体装置及其制造方法
公开(公告)号：US06420763B1
公开(公告)日：2002-07-16
申请号：US08917528
申请日：1997-08-26
申请人： Tomohiro Yamashita , Shigeki Komori , Masahide Inuishi
发明人： Tomohiro Yamashita , Shigeki Komori , Masahide Inuishi
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L27/1052
摘要： A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.
摘要翻译：半导体衬底是第一导电类型并且具有逆向阱杂质浓度。在半导体衬底的主表面上形成第一导电类型并具有杂质浓度峰值的第二杂质浓度的第一种。第三杂质浓度的第一杂质层与逆行井的下侧接触。第三杂质浓度小于第一杂质浓度和第二杂质浓度的杂质浓度峰值。在逆行井上形成一个元件。

4. 发明授权

US5852327A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5852327A
公开(公告)日：1998-12-22
申请号：US709592
申请日：1996-09-09
申请人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
发明人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
IPC分类号： H01L21/768 , H01L23/48 , H01L29/78
CPC分类号： H01L21/74
摘要： In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.
摘要翻译：在半导体器件的半导体衬底中，形成与衬底相同导电类型的多个杂质层。相反导电类型的杂质区域从半导体衬底的主表面穿透至少一个杂质层至一定的深度。杂质区域的底表面在杂质浓度较低的杂质层之间终止。接触导体从杂质区域引出。

5. 发明授权

US5369297A Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof 失效
标题翻译：包含氧化硅膜和氮化氧化膜作为栅极绝缘膜的场效应晶体管及其制造方法
公开(公告)号：US5369297A
公开(公告)日：1994-11-29
申请号：US930932
申请日：1992-08-18
申请人： Shigeru Kusunoki , Masahide Inuishi
发明人： Shigeru Kusunoki , Masahide Inuishi
IPC分类号： H01L21/266 , H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28185 , H01L21/266 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7836 , H01L29/78621 , Y10S257/90
摘要： An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.
摘要翻译：一种N型场效应晶体管，其具有对热载流子的较高的电阻率，并且即使在低栅极电压下使用时也具有更高的电流处理能力，并且提供了制造这种晶体管的方法。在排水雪崩热载体注入区域上形成氮化氧化物膜。与氧化硅膜相比，氮化氧化物膜对排水雪崩热载流子具有高度阻力。氧化硅膜形成在通道热电子注入区域上。与氮化氧化物膜相比，氧化硅膜对沟道热电子具有高度的阻力。栅绝缘膜的主要部分是氧化硅膜。与氮化氧化物膜相比，氧化硅膜在低栅极电压下表现出更高的电流处理能力。

6. 发明授权

US5089865A MIS semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5089865A
公开(公告)日：1992-02-18
申请号：US462536
申请日：1990-01-03
申请人： Katsuyoshi Mitsui , Masahide Inuishi
发明人： Katsuyoshi Mitsui , Masahide Inuishi
IPC分类号： H01L21/336 , H01L29/78 , H01L29/10 , H01L29/04
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.
摘要翻译：在具有LDD和自对准硅化物结构的MIS晶体管中，高和低杂质浓度源极/漏极区域之间的边界位置和源极/漏极区域上的自对准硅化物层的位置在制造期间被独立地控制，使用双门侧壁结构。因此，改善的MIS晶体管相对于双栅极侧壁结构的界面在其与控制栅电极之间或之后的高杂质浓度源极/漏极区域之间具有边界。

7. 发明授权

US5023682A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5023682A
公开(公告)日：1991-06-11
申请号：US370662
申请日：1989-06-23
申请人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
发明人： Masahiro Shimizu , Hiroki Shimano , Masahide Inuishi , Katsuhiro Tsukamoto
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/00 , H01L27/108
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), thin p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness. Films 16 and 17 are added to prevent an increase in diffusion resistance of the regions (6, 7) and the interconnection resistance of the second gate electrode (3). An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner.A bit line is formed on the semiconductor region and connected thereto. An interlayer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n.sup.+ -type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorous oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
摘要翻译：半导体存储器件包括p型半导体衬底（1），形成在其上的薄p +型区域（15,80），被p +型区域（15,80）包围的n +型区域（6,7），形成在n +型区域（6）的电荷存储区域上的第一栅电极（2）和形成在p +型区域（80）上并用作字线的第二栅电极（3）。 p +型区域（15,80）防止电子从α射线诱发的电子 - 空穴对中流出，以防止软错误的发生。有利地，用于控制装置的传输门的阈值电压的薄p +层被扩展，并且还用于防止这种软错误，从而为装置提供减少的体积。为了进一步减小体积，n +型区域（6,7）的厚度也减小。加入薄膜16和17以防止区域（6,7）的扩散阻力的增加和第二栅电极（3）的互连电阻的增加。在第二栅电极（3）的侧壁上形成氧化膜（16），在n +型区域（6,7）上形成硅化钛膜（17），硅化钛膜（18）为以自对准的方式形成在第二栅电极（3）上。在半导体区域上形成位线并与其连接。可选地，在位线和位于半导体n +型区域上的难熔金属硅化物膜之间形成层间绝缘膜。层间绝缘膜优选包含氧化硅膜或氧化磷膜。最后，可选地在位线上形成保护膜。保护膜优选由具有低介电常数的材料制成。

8. 发明授权

US4702797A Method of manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US4702797A
公开(公告)日：1987-10-27
申请号：US943053
申请日：1986-12-18
申请人： Hiroki Shimano , Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
发明人： Hiroki Shimano , Masahiro Shimizu , Katsuhiro Tsukamoto , Masahide Inuishi
IPC分类号： H01L27/10 , G11C11/34 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/08 , H01L29/10 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L27/1085 , H01L27/10805 , H01L29/0847 , H01L29/1083 , Y10S438/953
摘要： A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.+ -type regions (80a, 81a), so that operation of a parasitic pnp transistor is not caused.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在p型半导体衬底（1）上形成存储单元部分（2,4,6,11），形成栅极绝缘膜（5）和栅电极（3））各自具有比原始宽度大约1μm的离子注入p型杂质，利用栅极绝缘膜（5）和栅电极（3）作为掩模，形成p +型区域（将栅极绝缘体膜（5）和栅电极（3）的侧壁蚀刻到原始宽度，然后将这些区域的n型杂质离子注入作为掩模，形成n +型区域（80,81），并对这些区域（80,81,120,121）进行热处理，以形成区域（80a，81a，120a，121a）。 p +型区域（120a，121a）防止电子从由α射线诱发的电子 - 空穴对中流出，以防止发生软错误。 p +型区域（120a，121a）位于n +型区域（80a，81a）内部，从而不产生寄生pnp晶体管的操作。

9. 发明授权

US5554876A Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof 失效
标题翻译：包含氧化硅膜和氮化氧化膜作为栅极绝缘膜的场效应晶体管及其制造方法
公开(公告)号：US5554876A
公开(公告)日：1996-09-10
申请号：US292591
申请日：1994-08-16
申请人： Shigeru Kusunoki , Masahide Inuishi
发明人： Shigeru Kusunoki , Masahide Inuishi
IPC分类号： H01L21/266 , H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28185 , H01L21/266 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7836 , H01L29/78621 , Y10S257/90
摘要： An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.
摘要翻译：一种N型场效应晶体管，其具有对热载流子的较高的电阻率，并且即使在低栅极电压下使用时也具有更高的电流处理能力，并且提供了制造这种晶体管的方法。在排水雪崩热载体注入区域上形成氮化氧化物膜。与氧化硅膜相比，氮化氧化物膜对排水雪崩热载流子具有高度阻力。氧化硅膜形成在通道热电子注入区域上。与氮化氧化物膜相比，氧化硅膜对沟道热电子具有高度的阻力。栅绝缘膜的主要部分是氧化硅膜。与氮化氧化物膜相比，氧化硅膜在低栅极电压下表现出更高的电流处理能力。

10. 发明授权

US5200353A Method of manufacturing a semiconductor device having trench capacitor 失效
标题翻译：制造具有沟槽电容器的半导体器件的方法
公开(公告)号：US5200353A
公开(公告)日：1993-04-06
申请号：US754296
申请日：1991-09-04
申请人： Masahide Inuishi
发明人： Masahide Inuishi
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： A semiconductor memory device comprises a semiconductor substrate having a trench, first polysilicon serving as a charge storage region formed through an insulating film in an inner portion of the trench, and second polysilicon serving as a capacitor electrode formed through an insulating film inside of the first polysilicon. An impurity contact region connects the charge storage region to a transfer gate transistor in the surface adjacent the trench so that information charges are transferred. A method for manufacturing such a semiconductor memory device includes forming a trench in the major surface of the semiconductor substrate and forming a first insulating layer in an inner portion of the trench. On at least one sidewall of the trench, the first insulating layer begins at a distance below the upper end of the trench. The impurity contact region is formed by obliquely implanting ions in the region of the sidewall above the first insulating layer and in a portion of the major surface of the substrate. The first polysilicon layer, which serves as the charge storage region of the capacitor, is formed in the trench in contact with the impurity contact region. The insulating film and the second polysilicon electrode of the capacitor are then formed on the first polysilicon layer.
摘要翻译：半导体存储器件包括具有沟槽的半导体衬底，用作在沟槽内部通过绝缘膜形成的电荷存储区域的第一多晶硅，以及用作电容器电极的第二多晶硅，其通过第一多晶硅杂质接触区域将电荷存储区域连接到与沟槽相邻的表面中的传输栅极晶体管，从而传送信息电荷。一种用于制造这种半导体存储器件的方法包括在半导体衬底的主表面上形成沟槽，并在沟槽的内部形成第一绝缘层。在沟槽的至少一个侧壁上，第一绝缘层在沟槽的上端下方的距离处开始。杂质接触区域通过在第一绝缘层上方的侧壁的区域中以及衬底的主表面的一部分中倾斜地注入离子而形成。作为电容器的电荷存储区域的第一多晶硅层形成在与杂质接触区域接触的沟槽中。然后在第一多晶硅层上形成电容器的绝缘膜和第二多晶硅电极。

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