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1. 发明授权

US08912014B1 Controlling the latchup effect 有权
标题翻译：控制闭锁效果
公开(公告)号：US08912014B1
公开(公告)日：2014-12-16
申请号：US11333208
申请日：2006-01-18
申请人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
发明人： Chuan Lin , Dong-Hyuk Ju , Imran Khan , Jun Kang , Shibly S. Ahmed
IPC分类号： H01L21/66
CPC分类号： G01R31/27 , G01R31/2884 , H01L22/12 , H01L22/34 , H01L27/0921
摘要： A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.
摘要翻译：一种方法包括在源极区域或漏极区域中的至少一个与阱接触区域之间改变间隔以产生一组构型。该方法还包括确定闭锁对每个配置的影响。

2. 发明授权

US08536011B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US08536011B2
公开(公告)日：2013-09-17
申请号：US13074836
申请日：2011-03-29
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/336 , H01L21/44 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

3. 发明授权

US07939440B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US07939440B2
公开(公告)日：2011-05-10
申请号：US11152375
申请日：2005-06-15
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/425 , H01L21/44
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

4. 发明申请

US20070052002A1 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US20070052002A1
公开(公告)日：2007-03-08
申请号：US11152375
申请日：2005-06-15
申请人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

5. 发明授权

US07084458B1 Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 有权
标题翻译：半导体器件具有三重LDD结构和较低的栅极电阻，由单一的注入工艺形成
公开(公告)号：US07084458B1
公开(公告)日：2006-08-01
申请号：US11120690
申请日：2005-05-02
申请人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
发明人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L29/66598
摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
摘要翻译：公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

6. 发明授权

US06939770B1 Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 失效
标题翻译：制造具有三重LDD结构的半导体器件的方法和用单个注入工艺形成的较低的栅极电阻
公开(公告)号：US06939770B1
公开(公告)日：2005-09-06
申请号：US10618514
申请日：2003-07-11
申请人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
发明人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/66598
摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
摘要翻译：公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

7. 发明申请

US20050235027A1 Arithmetic and logic unit using half adder 失效
标题翻译：使用半加法器的算术和逻辑单元
公开(公告)号：US20050235027A1
公开(公告)日：2005-10-20
申请号：US10849665
申请日：2004-05-20
申请人： Ku Jung , Jun Kang , Alex Kirichenko , Saad Sarwana
发明人： Ku Jung , Jun Kang , Alex Kirichenko , Saad Sarwana
IPC分类号： G06F7/50 , G06F7/00 , G06F7/57
CPC分类号： G06F7/57
摘要： The present invention discloss an ALU that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor rapid single flux quantum logic device. The ALU using a half adder includes a half adder using a superconductor rapid single flux quantum logic device as a logic circuit, and a switching unit that has input ports respectively connected to a sum output port and a carry output port of the half adder and is operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using output signals of the half adder. The switching unit includes a first switch having an input port connected to the sum output port of the half adder, a second switch having an input port connected to the carry output port of the half adder and an output port connected to an output port of the first switch, and a third switch having an input port connected to the carry output port of the half adder.
摘要翻译：本发明可以使用使用超导体快速单通量量子逻辑器件的半加法器来操作为“或”门，“与”门，“加法器”门和“异或”门“的ALU。使用半加法器的ALU包括使用超导体快速单通量量子逻辑器件作为逻辑电路的半加法器，以及具有分别连接到半加法器的和输出端口和进位输出端口的输入端口的开关单元，并且是作为或门，与门，加法器门和使用半加法器的输出信号的异或门运算。开关单元包括具有连接到半加法器的和输出端口的输入端口的第一开关，具有连接到半加法器的进位输出端口的输入端口的第二开关和连接到半加法器的输出端口的输出端口第一开关和具有连接到半加法器的进位输出端口的输入端口的第三开关。

8. 发明申请

US20050071987A1 Lithium secondary battery 失效
公开(公告)号：US20050071987A1
公开(公告)日：2005-04-07
申请号：US10997472
申请日：2004-11-23
申请人： Jin Kim , Jun Kang , Hak Kim , Jong Kim
发明人： Jin Kim , Jun Kang , Hak Kim , Jong Kim
IPC分类号： H01M4/38 , H01M4/505 , H01M4/525 , H01M4/58 , H01M4/60 , H01M6/16 , H01M10/04 , H01M10/05 , H01M10/052 , H01M10/0565 , H01M10/0567 , H01M10/0568 , H01M10/0569 , H01M10/058 , H01M10/44 , H01M10/40
CPC分类号： H01M10/0525 , H01M4/131 , H01M4/133 , H01M4/505 , H01M4/525 , H01M10/0567 , H01M10/0569 , H01M10/058 , H01M10/446 , H01M2300/0025 , H01M2300/0042 , Y10T29/49108
摘要： Disclosed is a lithium secondary battery comprising a positive electrode including a material that is capable of reversible intercalation/deintercalation of lithium ions as a positive active material; a negative electrode including a material that is capable of reversible intercalation/deintercalation of lithium ions as a negative active material; and an electrolyte including a lithium salt, a carbonate-based organic solvent, and an isoxazole compound of the following formula (1):

9. 发明授权

US06903407B1 Non volatile charge trapping dielectric memory cell structure with gate hole injection erase 有权
标题翻译：具有栅极空穴注入擦除的非易失性电荷捕获介质存储单元结构
公开(公告)号：US06903407B1
公开(公告)日：2005-06-07
申请号：US10684890
申请日：2003-10-14
申请人： Jun Kang
发明人： Jun Kang
IPC分类号： H01L21/28 , H01L29/423 , H01L29/792 , H01L29/788
CPC分类号： H01L29/42332 , H01L21/28282 , H01L29/7923
摘要： A dielectric memory cell comprises a substrate which includes a source region, a drain region, and a channel region positioned there between. A multilevel charge trapping dielectric is positioned on the surface of the substrate and a control gate is positioned on the surface of the dielectric and is positioned over and aligned with the channel region. The multilevel charge trapping dielectric includes a tunneling dielectric layer, a charge trapping dielectric layer, and a top dielectric layer. The tunneling dielectric layer comprises a first dielectric material having a wide band gap between a tunneling dielectric layer valance band Fermi level and a tunneling dielectric layer conduction band Fermi level. The top dielectric layer comprises a second dielectric material having a valance band Fermi level approximately equal to the tunneling dielectric layer valance band Fermi level and having a conduction band Fermi level greater than the tunneling dielectric layer conduction band Fermi level. The charge trapping layer is positioned between the bottom layer and the top layer of a third dielectric with charge trapping properties.
摘要翻译：介质存储单元包括衬底，其包括源极区，漏极区和位于其间的沟道区。多层电荷捕获电介质位于衬底的表面上，并且控制栅极位于电介质的表面上并且被定位在沟道区上方并与沟道区对准。多电荷电荷俘获电介质包括隧道介电层，电荷俘获电介质层和顶部电介质层。隧道介电层包括在隧道介电层价带费米子层和隧道电介质层导带费米能级之间具有宽带隙的第一介电材料。顶部电介质层包括第二电介质材料，其具有大致等于隧穿介电层价带费米能级的价带费米子电平，并且具有大于隧道电介质层导带费米能级的导带费米能级。电荷捕获层位于具有电荷捕获性质的第三电介质的底层和顶层之间。

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