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1. 发明申请

US20070090360A1 Blanket implant diode 审中-公开
标题翻译：毯式植入二极管
公开(公告)号：US20070090360A1
公开(公告)日：2007-04-26
申请号：US11415522
申请日：2006-05-02
申请人： Sheng-Huei Dai , Ya-Chin King , Chun-Jen Huang , L.C. Kao
发明人： Sheng-Huei Dai , Ya-Chin King , Chun-Jen Huang , L.C. Kao
IPC分类号： H01L29/04 , H01L21/00 , H01L29/15 , H01L29/10 , H01L31/00 , H01L31/036
CPC分类号： H01L29/8611 , H01L29/66136
摘要： Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially etched away from a portion of the P− region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P− region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.
摘要翻译：可以用于瞬态电压抑制的毯式注入二极管，其具有在衬底的顶表面附近注入N型掺杂剂覆盖层注入的P +衬底，形成P-区。在P区附近层叠氧化物掩模。氧化物掩模被部分地蚀刻离开P-区域的一部分，产生蚀刻区域。将N型主要功能植入物注入到蚀刻区域中，在P +衬底上方形成N +区域并邻近P-区域。并且，在蚀刻区域中的氧化物掩模上方形成金属以形成电极。端子可以电连接到P-N结的两侧。还提供了制造和使用本发明的方法和用于瞬态电压抑制的方法。

2. 发明申请

US20080036048A1 Semiconductor junction device having reduced leakage current and method of forming same 审中-公开
标题翻译：具有减小的漏电流的半导体接合装置及其形成方法
公开(公告)号：US20080036048A1
公开(公告)日：2008-02-14
申请号：US11827594
申请日：2007-07-12
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L21/76 , H01L29/12
CPC分类号： H01L21/76216
摘要： A semiconductor junction device includes a semiconductor substrate of a first conductivity type and a junction layer formed on the substrate which has a second conductivity type. A field reducing region of the first conductivity type surrounds a periphery of the junction layer and extends under a peripheral portion of the junction layer. An insulating layer is provided on the field reducing region and a metal layer overlies the junction layer and the insulating layer.
摘要翻译：半导体结器件包括第一导电类型的半导体衬底和形成在具有第二导电类型的衬底上的接合层。第一导电类型的场减少区围绕结层的周边并在结层的周边部分的下方延伸。绝缘层设置在场致还区上，金属层覆盖在接合层和绝缘层上。

3. 发明申请

US20080036047A1 Low voltage transient voltage suppressor with reduced breakdown voltage 有权
标题翻译：具有降低击穿电压的低压瞬态电压抑制器
公开(公告)号：US20080036047A1
公开(公告)日：2008-02-14
申请号：US11827463
申请日：2007-07-11
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/861 , H01L29/66136
摘要： A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.
摘要翻译：半导体结器件包括具有预选极性的低电阻率半导体材料的衬底。锥形凹槽延伸到衬底中，并且从衬底的上表面向下延伸到内部渐缩。半导体层设置在凹槽内并在衬底的上表面上方延伸。半导体层的极性与基板的极性相反。金属层覆盖半导体层。

4. 发明授权

US07737533B2 Low voltage transient voltage suppressor with tapered recess extending into substrate of device allowing for reduced breakdown voltage 有权
标题翻译：低电压瞬态电压抑制器，具有延伸到器件基板的锥形凹槽，允许降低击穿电压
公开(公告)号：US07737533B2
公开(公告)日：2010-06-15
申请号：US11827463
申请日：2007-07-11
申请人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
发明人： Sheng-Huei Dai , Ya-Chin King , Hai-Ning Wang , Ming-Tai Chiang
IPC分类号： H01L29/26
CPC分类号： H01L29/861 , H01L29/66136
摘要： A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.
摘要翻译：半导体结器件包括具有预选极性的低电阻率半导体材料的衬底。锥形凹槽延伸到衬底中，并且从衬底的上表面向下延伸到内部渐缩。半导体层设置在凹槽内并在衬底的上表面上方延伸。半导体层的极性与基板的极性相反。金属层覆盖半导体层。

5. 发明申请

US20130052781A1 Method of Forming Non-planar FET 有权
标题翻译：形成非平面FET的方法
公开(公告)号：US20130052781A1
公开(公告)日：2013-02-28
申请号：US13218438
申请日：2011-08-25
申请人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
发明人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
IPC分类号： H01L21/8232
CPC分类号： H01L29/7851 , H01L21/845 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
摘要翻译：提供一种形成非平面FET的方法。提供基板。在衬底上限定有源区和周边区。在基板的有源区域中形成多个VSTI。去除每个VSTI的一部分以露出衬底的侧壁的一部分。然后，在衬底上形成导体层，然后将其图案化以在周边区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。最后，源极/漏极区域形成在非平面FET栅极的两侧。

6. 发明申请

US20120299099A1 FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US20120299099A1
公开(公告)日：2012-11-29
申请号：US13116018
申请日：2011-05-26
申请人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/786 , H01L21/3205
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

7. 发明授权

US08772860B2 FINFET transistor structure and method for making the same 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US08772860B2
公开(公告)日：2014-07-08
申请号：US13116018
申请日：2011-05-26
申请人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

8. 发明授权

US08691651B2 Method of forming non-planar FET 有权
标题翻译：形成非平面FET的方法
公开(公告)号：US08691651B2
公开(公告)日：2014-04-08
申请号：US13218438
申请日：2011-08-25
申请人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
发明人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/845 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
摘要翻译：提供一种形成非平面FET的方法。提供基板。在衬底上限定有源区和周边区。在基板的有源区域中形成多个VSTI。去除每个VSTI的一部分以露出衬底的侧壁的一部分。然后，在衬底上形成导体层，然后将其图案化以在外围区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。最后，源极/漏极区域形成在非平面FET栅极的两侧。

9. 发明授权

US09105660B2 Fin-FET and method of forming the same 有权
标题翻译： Fin-FET及其形成方法
公开(公告)号：US09105660B2
公开(公告)日：2015-08-11
申请号：US13211334
申请日：2011-08-17
申请人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
发明人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
IPC分类号： H01L29/66 , H01L21/02 , H01L21/20 , H01L29/78
CPC分类号： H01L29/7853 , H01L21/02647 , H01L21/2022 , H01L29/1054 , H01L29/16 , H01L29/66795 , H01L29/7842 , H01L29/785 , H01L2029/7858
摘要： A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
摘要翻译：提供了形成Fin-FET的方法。提供衬底，然后在其上形成掩模层。在衬底和掩模层中形成第一沟槽。在第一沟槽中形成半导体层。接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。最后，在鳍结构上形成栅极层。

10. 发明申请

US20130043506A1 Fin-FET and Method of Forming the Same 有权
标题翻译： Fin-FET及其形成方法
公开(公告)号：US20130043506A1
公开(公告)日：2013-02-21
申请号：US13211334
申请日：2011-08-17
申请人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
发明人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/7853 , H01L21/02647 , H01L21/2022 , H01L29/1054 , H01L29/16 , H01L29/66795 , H01L29/7842 , H01L29/785 , H01L2029/7858
摘要： A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
摘要翻译：提供了形成Fin-FET的方法。提供衬底，然后在其上形成掩模层。在衬底和掩模层中形成第一沟槽。在第一沟槽中形成半导体层。接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。最后，在鳍结构上形成栅极层。

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