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    • 1. 发明授权
    • Do-It-Yourself photo realistic talking head creation system and method
    • 自制自己照片真实的说话头创建系统和方法
    • US08553037B2
    • 2013-10-08
    • US12296912
    • 2006-04-10
    • Shawn SmithMichael CheikyPeter Gately
    • Shawn SmithMichael CheikyPeter Gately
    • G06T13/00G06F17/00
    • G06T13/40G06T2200/24
    • A do-it-yourself photo realistic talking head creation system comprising: a template; handheld device comprising display and video camera having an image output signal of a subject; a computer having a mixer program for mixing the template and image output signal of the subject into a composite image, and an output signal representational of the composite image; a computer adapted to communicate the composite image signal to the display for display to the subject as a composite image; the display and the video camera adapted to allow the video camera to collect the image of the subject, the subject to view the composite image, and the subject to align the image of the subject with the template; storage means having an input for receiving the output signal of the video camera representational of the collected image of the subject and storing the image of the subject substantially aligned with the template.
    • 一个自己动手的照片真实的头脑创作系统,包括:一个模板; 手持式装置,包括具有被摄体的图像输出信号的显示器和摄像机; 具有用于将所述对象的模板和图像输出信号混合成合成图像的混合程序的计算机和表示所述合成图像的输出信号; 计算机,适于将所述合成图像信号传送到所述显示器,以作为合成图像显示给所述对象; 所述显示器和所述摄像机适于允许所述摄像机收集所述被摄体的图像,所述对象以观看所述合成图像,并且所述对象将所述被摄体的图像与所述模板对准; 存储装置具有用于接收所述摄像机的输出信号的输入,所述输出信号代表所述被摄体的所收集的图像,并且存储所述对象的图像与所述模板基本对齐。
    • 2. 发明申请
    • Do-It-Yourself Photo Realistic Talking Head Creation System and Method
    • 做自己的照片现实的谈话头创造系统和方法
    • US20100007665A1
    • 2010-01-14
    • US12296912
    • 2006-04-10
    • Shawn SmithMichael CheikyPeter Gately
    • Shawn SmithMichael CheikyPeter Gately
    • G06T15/70
    • G06T13/40G06T2200/24
    • A do-it-yourself photo realistic talking head creation system comprising: a template; handheld device comprising display and video camera having an image output signal of a subject; a computer having a mixer program for mixing the template and image output signal of the subject into a composite image, and an output signal representational of the composite image; a computer adapted to communicate the composite image signal to the display for display to the subject as a composite image; the display and the video camera adapted to allow the video camera to collect the image of the subject, the subject to view the composite image, and the subject to align the image of the subject with the template; storage means having an input for receiving the output signal of the video camera representational of the collected image of the subject and storing the image of the subject substantially aligned with the template.
    • 一个自己动手的照片真实的头脑创作系统,包括:一个模板; 手持式装置,包括具有被摄体的图像输出信号的显示器和摄像机; 具有用于将所述对象的模板和图像输出信号混合成合成图像的混合程序的计算机和表示所述合成图像的输出信号; 计算机,适于将所述合成图像信号传送到所述显示器,以作为合成图像显示给所述对象; 所述显示器和所述摄像机适于允许所述摄像机收集所述对象的图像,所述对象以观看所述合成图像,并且所述对象将所述对象的图像与所述模板对准; 存储装置具有用于接收所述摄像机的输出信号的输入,所述输出信号代表所述被摄体的所收集的图像,并且存储所述对象的图像与所述模板基本对齐。
    • 4. 发明申请
    • Two-component, rectifying-junction memory element
    • 双组分整流结存储元件
    • US20050195640A1
    • 2005-09-08
    • US10998187
    • 2004-11-26
    • Shawn SmithStephen Forrest
    • Shawn SmithStephen Forrest
    • G11C13/00G11C13/02G11C17/16H01L20060101H01L27/28H01L51/00H01L51/05H01L51/30
    • H01L51/0587B82Y10/00G11C13/0009G11C13/0014G11C13/0016G11C17/16G11C2213/72G11C2216/26H01L27/285H01L51/0037
    • Embodiments of the present invention are directed to low complexity, efficient, two-component memory elements for use in low-cost, robust, and reliable WORM memories. The memory element of one embodiment is an organic-on-inorganic heterojunction diode comprising an organic-polymer layer joined to a doped, inorganic semiconductor layer. The organic polymer layer serves both as one later of a two-later, semiconductor-based diode, as well as a fuse. Application of a voltage greater than a threshold WRITE voltage for a period of time greater than a threshold time interval for a WRITE-voltage pulse irreversibly and dramatically increases the resistivity of the organic polymer layer. The memory element that represents one embodiment of the present invention is more easily manufactured than previously described, separate-fuse-and-diode memory elements, and has the desirable characteristics of being switchable at lower voltages and with significantly shorter-duration WRITE-voltage pulses than the previously described memory elements.
    • 本发明的实施例涉及用于低成本,稳健和可靠的WORM存储器的低复杂度,高效率的双分量存储器元件。 一个实施方案的存储元件是无机异源结二极管,其包含连接到掺杂的无机半导体层的有机聚合物层。 有机聚合物层同时用作两个以后的半导体二极管以及一个保险丝。 施加大于阈值写入电压的电压大于写电压脉冲的阈值时间间隔的时间段不可逆地显着增加有机聚合物层的电阻率。 代表本发明的一个实施例的存储元件比先前描述的更容易制造,分离的熔丝和二极管存储元件,并且具有可在较低电压下切换并具有显着更短持续时间的写电压脉冲的期望特性 比之前描述的存储器元件。
    • 8. 发明授权
    • IC test software system for mapping logical functional test data of logic integrated circuits to physical representation
    • 用于将逻辑集成电路的逻辑功能测试数据映射到物理表示的IC测试软件系统
    • US06185707B2
    • 2001-02-06
    • US09192164
    • 1998-11-13
    • Shawn SmithHari BalachandranJason Parker
    • Shawn SmithHari BalachandranJason Parker
    • G01R3128
    • G01R31/318307G01R31/2834
    • The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether “in-line” inspection data can account for a given failure. These nodes may then be crossmapped from the circuit design onto the chip's layout for each of multiple photomask layers within the design. Detailed failure data is gathered and stored at the wafer stage as part of a comprehensive program rather than on an as-needed basis at the packaged part stage. A voluminous amount of high-quality data is therefore obtained in an entirely automated fashion, as opposed to obtaining a comparatively minuscule amount of lesser-quality data in an exceedingly laborious fashion.
    • 本发明一般地利用上述能力,通过翻译通过模拟模型的数字逻辑芯片的功能测试数据来确定和显示对应于网络名称的X,Y位置,该仿真模型识别一个或多个缺陷网 的芯片。 针对上述类型的数据库处理有缺陷的网络,以获得这些网络的X,Y坐标数据,允许它们作为芯片布局上的物理轨迹记录数据。 根据示例性实施例,通过从功能测试器获取输出并将其从故障扫描链的列表转换成可疑的网表节点列表来执行该映射。 然后将可疑网表节点的X,Y坐标识别并存储在数据库中,为故障分析和产量增强工程师提供执行故障分析的起点,并立即了解“在线”检查数据是否可以解决给定故障 。 然后,可以将这些节点从电路设计中交叉映射到设计中的每个多个光掩模层的芯片布局上。 收集并存储详细的故障数据,作为综合程序的一部分,而不是在打包的部分阶段根据需要进行存储。 因此,以完全自动化的方式获得大量的高质量数据,而不是以非常费力的方式获得相对较少量的较差质量的数据。