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1. 发明授权

US06501734B1 Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port 有权
标题翻译：网络交换机中的装置和方法，用于在千兆端口和扩展端口之间动态分配存储器接口槽
公开(公告)号：US06501734B1
公开(公告)日：2002-12-31
申请号：US09317150
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04J116
CPC分类号： H04L49/103 , H04L49/254 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/90 , H04L49/901
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.
摘要翻译：具有根据以太网（IEEE 802.3）协议的具有各个网络节点的数据分组全双工通信的交换机端口的网络交换机动态地在高数据速率端口之间分配外部存储器带宽时隙。外部存储器接口确定高数据速率端口是否对带宽槽进行请求，如果发出请求则确定该请求。时隙是从所选择的组中获取的，该组是总时隙数的子集。如果没有对插槽进行请求，则外部存储器接口将插槽分配给另一个高数据速率端口。网络交换机中的较低数据速率端口从这些时隙中分配固定时隙，而不是在所选择的时隙组内。高数据速率端口之间的带宽时隙的动态分配使得能够有效地利用有限的存储器带宽资源。

2. 发明授权

US06658015B1 Multiport switch with plurality of logic engines for simultaneously processing different respective data frames 失效
标题翻译：具有多个逻辑引擎的多端口交换机，用于同时处理不同的相应数据帧
公开(公告)号：US06658015B1
公开(公告)日：2003-12-02
申请号：US09321623
申请日：1999-05-28
申请人： Shashank Merchant , Chandan Egbert , John M. Chiang
发明人： Shashank Merchant , Chandan Egbert , John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L49/103 , H04L49/3027 , H04L49/354 , H04L49/90
摘要： A network switch configured for switching data packets across multiple ports uses decision making device to generate frame forwarding information. The decision making device employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The decision making device also includes a memory to store frame headers to minimize the signaling between the decision making device and the receive devices.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用决策设备生成帧转发信息。决策设备采用模块化架构，可以同时处理数据帧并提高数据吞吐量。决策设备还包括存储器以存储帧头以最小化决策设备和接收设备之间的信令。

3. 发明授权

US06442137B1 Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port 失效
标题翻译：用于交换千兆端口和扩展端口之间的存储器访问槽的网络交换机中的装置和方法
公开(公告)号：US06442137B1
公开(公告)日：2002-08-27
申请号：US09317143
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04L522
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/90 , H04L49/9031 , H04L49/9078
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.
摘要翻译：网络交换机具有用于根据以太网（IEEE 802.3）协议的具有各网络节点的数据分组全双工通信的交换机端口，该协议基于网络流量的比较量在高数据速率端口之间分配规定数量的外部存储器带宽时隙各个端口。外部存储器接口中的调度器根据规定的顺序，初始地将存储器访问时隙分配给相应的高数据速率端口。如果调度器随后检测到具有较少时隙的端口上的网络数据流量高于具有更多时隙的端口上的流量，则这些时隙在高数据速率端口之间交换。此外，高数据速率端口之一中的时钟多路复用器根据分配给该端口的时隙数来调整端口的数据速率。在高数据速率端口之间交换带宽时隙以及端口时钟速率的调整使得能够有效地使用有限的存储器带宽资源。

4. 发明授权

US07031305B1 Apparatus and method for programmable memory access slot assignment 有权
标题翻译：可编程存储器存取槽分配的装置和方法
公开(公告)号：US07031305B1
公开(公告)日：2006-04-18
申请号：US09317156
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04L12/28
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/354
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.
摘要翻译：根据以太网（IEEE 802.3）协议，具有根据可编程信息灵活地分配存储器访问时隙以访问外部存储器的数据分组与各网络节点全双工通信的交换机端口的网络交换机。外部存储器接口中的调度器根据从外部可编程数据存储设备写入指配表存储器的编程序列，将存储器访问时隙分配给相应的网络交换机端口。

5. 发明授权

US06813266B1 Pipelined access to address table in a network switch 有权
标题翻译：流水线访问网络交换机中的地址表
公开(公告)号：US06813266B1
公开(公告)日：2004-11-02
申请号：US09315851
申请日：1999-05-21
申请人： John M. Chiang , Shashank Merchant
发明人： John M. Chiang , Shashank Merchant
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L2012/5624 , H04L2012/5652 , H04L2012/5679 , H04L2012/568 , H04L2012/5681
摘要： A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用决策逻辑生成帧转发信息。决策逻辑采用流水线架构，可以同时处理多个数据帧，从而提高数据吞吐量。决策逻辑还可以访问存储数据转发信息的地址查找表。仲裁电路为决策设备提供在备用时隙中对地址表的自动访问，并且使得其他电路能够在预定时隙中访问地址表。

6. 发明授权

US06816488B1 Apparatus and method for processing data frames in a network switch 有权
标题翻译：用于处理网络交换机中数据帧的装置和方法
公开(公告)号：US06816488B1
公开(公告)日：2004-11-09
申请号：US09315855
申请日：1999-05-21
申请人： Shashank Merchant , John M. Chiang
发明人： Shashank Merchant , John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L45/745 , H04L49/103 , H04L49/352 , H04L49/354
摘要： A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding decisions. The switch buffers data frame header information in an internal memory for processing by the decision making logic. The switch employs a modular architecture that enables the decision making logic to perform its processing independently from other logic functions of the switch.
摘要翻译：配置为跨多个端口切换数据分组的网络交换机使用决策逻辑来生成帧转发决策。该开关将数据帧头信息缓冲在内部存储器中，以由决策逻辑进行处理。交换机采用模块化架构，使决策逻辑能够独立于交换机的其他逻辑功能执行其处理。

7. 发明授权

US06535489B1 Method and apparatus in a network switch for handling link failure and link recovery in a trunked data path 有权
标题翻译：用于处理中继数据路径中的链路故障和链路恢复的网络交换机中的方法和装置
公开(公告)号：US06535489B1
公开(公告)日：2003-03-18
申请号：US09315854
申请日：1999-05-21
申请人： Shashank Merchant , Robert Williams , John M. Chiang , Ching Yu
发明人： Shashank Merchant , Robert Williams , John M. Chiang , Ching Yu
IPC分类号： G06F1110
CPC分类号： H04L45/245 , H04L41/0654 , H04L43/0817 , H04L45/28 , Y02D50/30
摘要： A network switch configured for switching data packets across multiple ports and for supporting trunked data paths uses an address table to generate frame forwarding information. When a link in a trunked data path experiences a change in its operating status, the trunk data path is reconfigured to reflect the current operating conditions, without reprogramming the address table or powering down the switch.
摘要翻译：配置为跨多个端口切换数据包并支持集群数据路径的网络交换机使用地址表来生成帧转发信息。当中继数据路径中的链路经历其操作状态的改变时，重新配置中继线数据路径以反映当前的工作状态，而不重新编程地址表或关闭交换机。

8. 发明授权

US06480490B1 Interleaved access to address table in network switching system 失效
标题翻译：交换机访问地址表
公开(公告)号：US06480490B1
公开(公告)日：2002-11-12
申请号：US09305662
申请日：1999-05-05
申请人： Shashank Merchant , John M. Chiang
发明人： Shashank Merchant , John M. Chiang
IPC分类号： H04L1228
CPC分类号： H04L45/742 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3027 , H04L49/351 , H04L49/354
摘要： A novel method of providing interleaved access to an address lookup table in a multiport communication system having a decision making engine for controlling data switching between receive and transmit ports. A source address (SA) lookup logic circuit and a destination address (DA) connected in a pipeline are enabled to alternately access the address table. An arbitration circuit provides the SA and DA logic circuits with automatic access to the address table in alternate time slots allocated to these logic circuits. Also, the arbitration circuit enables an aging circuit and a host processor to periodically access the address table in pre-selected time slots.
摘要翻译：一种提供对具有用于控制接收端口和发送端口之间的数据交换的决策引擎的多端口通信系统中的地址查找表的交织访问的新颖方法。源地址（SA）查找逻辑电路和连接在流水线中的目的地地址（DA）能够交替访问地址表。仲裁电路为SA和DA逻辑电路提供分配给这些逻辑电路的备用时隙中的地址表的自动访问。此外，仲裁电路使得老化电路和主机处理器能够以预先选择的时隙周期性地访问地址表。

9. 发明授权

US06335938B1 Multiport communication switch having gigaport and expansion ports sharing the same time slot in internal rules checker 有权
标题翻译：具有端口和扩展端口的多端口通信交换机在内部规则检查器中共享相同的时隙
公开(公告)号：US06335938B1
公开(公告)日：2002-01-01
申请号：US09304959
申请日：1999-05-05
申请人： John M. Chiang , Michael VengChong Lau , Shashank Merchant
发明人： John M. Chiang , Michael VengChong Lau , Shashank Merchant
IPC分类号： H04J316
CPC分类号： H04L49/45 , H04L49/1553 , H04L49/201 , H04L49/30 , H04L49/3009 , H04L49/352 , H04L49/354
摘要： A novel method of data processing in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. The receive ports include an expansion port for receiving data packets from another switching system, and a high-speed port for receiving data packets at a rate higher than data rates at regular receive ports. In accordance with the method of the present invention, data blocks representing received data packets are placed in a plurality of data queues corresponding to the plurality of the receive ports. The data queues are transferred in successive time slots to logic circuitry for determining at least one transmit port. The time slots assigned to each of the plurality of receive ports includes expansion port time slots assigned to the expansion port and high-speed time slots assigned to the high-speed port. The expansion and high-speed time slots are dynamically distributed between the expansion and high-speed ports in accordance with relative data traffic at the ports. In particular, non-requested high-speed port time slots may be allocated to the expansion port, if the number of requests for high-speed port time slots is less than the number of the high-speed time slots. Similarly, non-requested expansion port time slots may be allocated to the high-speed port, if the number of requests for expansion port time slots is less than the number of the expansion port time slots.
摘要翻译：一种具有用于控制接收端口与至少一个发送端口之间的数据转发的决策引擎的多端口数据交换系统中的数据处理的新颖方法。接收端口包括用于从另一交换系统接收数据分组的扩展端口和用于以高于常规接收端口的数据速率的速率接收数据分组的高速端口。根据本发明的方法，将表示接收到的数据分组的数据块放置在对应于多个接收端口的多个数据队列中。数据队列在连续的时隙中传送到用于确定至少一个发送端口的逻辑电路。分配给多个接收端口中的每一个的时隙包括分配给扩展端口的扩展端口时隙和分配给高速端口的高速时隙。根据端口上的相对数据流量，扩展和高速时隙在扩展端口和高速端口之间动态分配。特别地，如果高速端口时隙的请求数小于高速时隙的数量，则可以向扩展端口分配非请求的高速端口时隙。类似地，如果扩展端口时隙的请求数少于扩展端口时隙的数量，则可以将未请求的扩展端口时隙分配给高速端口。

10. 发明授权

US07991296B1 Method and apparatus for data frame synchronization and delineation 有权
标题翻译：用于数据帧同步和描绘的方法和装置
公开(公告)号：US07991296B1
公开(公告)日：2011-08-02
申请号：US11938019
申请日：2007-11-09
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04B10/00 , H04J14/00
CPC分类号： H04J3/0608
摘要： A circuit and method to synchronize with a data transmission having a plurality of data transmission frames each with a start boundary identified by a predetermined synchronization pattern, includes comparing sets of data within the data transmission to a predetermined synchronization pattern. A frame tracking signal is assigned to each one of the plurality of comparison results that indicates a match between a data pattern within one of the plurality of sets of data and the predetermined synchronization pattern, including matches that occur multiple times within a known duration of the data transmission frame duration. Based on each frame tracking signal assigned to a comparison result, the start boundary of the data transmission frames is searched. The start boundary may be search by monitoring successive occurrences of the predetermined synchronization pattern in the data transmission at intervals of the known data transmission frame duration for each data matching data pattern. If the predetermined synchronization pattern occurs successively in the data transmission, the associated data pattern is confirmed as the synchronization pattern in the data transmission, and synchronization with the data transmission is achieved.
摘要翻译：一种与具有多个数据传输帧的数据传输同步的电路和方法，每个数据传输帧具有由预定的同步模式识别的起始边界，包括将数据传输中的数据集合与预定的同步模式进行比较。帧跟踪信号被分配给多个比较结果中的每一个，其指示多个数据集合中的一个数据和预定同步模式之间的数据模式之间的匹配，包括在所述多个比较结果的已知持续时间内发生多次的匹配数据传输帧持续时间。基于分配给比较结果的每个帧跟踪信号，搜索数据传输帧的起始边界。可以通过以每个数据匹配数据模式的已知数据传输帧持续时间的间隔监视数据传输中的预定同步模式的连续出现来搜索起始边界。如果在数据传输中连续发生预定同步模式，则在数据传输中确认相关联的数据模式作为同步模式，并实现与数据传输的同步。

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