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1. 发明申请

US20100080305A1 Devices and Methods of Digital Video and/or Audio Reception and/or Output having Error Detection and/or Concealment Circuitry and Techniques 审中-公开
标题翻译：具有错误检测和/或隐藏电路和技术的数字视频和/或音频接收和/或输出的设备和方法
公开(公告)号：US20100080305A1
公开(公告)日：2010-04-01
申请号：US12565713
申请日：2009-09-23
申请人： Shaori Guo , Shi Cheng , Zhubing Yuan
发明人： Shaori Guo , Shi Cheng , Zhubing Yuan
IPC分类号： H04N7/64
CPC分类号： H04N21/4382 , H04N19/895 , H04N21/2383 , H04N21/2389 , H04N21/4385 , H04N21/4425
摘要： A device to output video and/or audio data (for example, corresponding to a selected channel which is one of a plurality of channels of a broadcast spectrum), the device comprising (i) baseband processor circuitry to demodulate a baseband signal into a data stream (for example, MPEG type data stream, such as an MPEG-2 transport or program data stream) having a plurality of packets including a plurality of video and/or audio packets wherein each video and/or audio packet includes video and/or audio payload, (ii) de-multiplexer circuitry, coupled to the baseband processor circuitry, to: (a) de-multiplex the data stream to obtain the video and/or audio payload of the plurality of video and/or audio packets, (b) detect and locate one or more errors in one or more of the video and/or audio packets, and (c) generate error characterization data (for example, information which is representative of the type of error and/or the location of the error in the video and/or audio payload) which is representative of or characterizes one or more errors in the one or more of the video and/or audio packets; and (iii) decoder circuitry, coupled to the de-multiplexer circuitry, to: (a) receive the video and/or audio payload and the error characterization data, and (b) conceal the one or more errors in the video and/or audio payload using the error characterization data.
摘要翻译：用于输出视频和/或音频数据的设备（例如，对应于作为广播频谱的多个频道之一的所选频道），该设备包括（i）基带处理器电路，用于将基带信号解调为数据具有包括多个视频和/或音频分组的多个分组的流（例如，MPEG类型数据流，诸如MPEG-2传输或节目数据流），其中每个视频和/或音频分组包括视频和/或音频有效载荷，（ii）耦合到基带处理器电路的去多路复用器电路，以：（a）解复用数据流以获得多个视频和/或音频分组的视频和/或音频有效载荷（ b）检测和定位一个或多个视频和/或音频分组中的一个或多个错误，以及（c）生成错误表征数据（例如，代表错误类型和/或位置的信息视频和/或音频有效载荷中的错误）呈现或表征一个或多个视频和/或音频分组中的一个或多个错误; 和（iii）耦合到解复用器电路的解码器电路，以：（a）接收视频和/或音频有效载荷和误差表征数据，以及（b）隐藏视频中的一个或多个错误和/或音频有效载荷使用错误表征数据。

2. 发明申请

US20110099330A1 MEMORY OPTIMIZATION FOR VIDEO PROCESSING 有权
标题翻译：用于视频处理的记忆优化
公开(公告)号：US20110099330A1
公开(公告)日：2011-04-28
申请号：US11575487
申请日：2005-09-16
申请人： Shaori Guo , Selliah Rathnam , Gwo Giun Lee
发明人： Shaori Guo , Selliah Rathnam , Gwo Giun Lee
IPC分类号： G06F12/08
CPC分类号： H04N19/426 , H04N7/014 , H04N19/433
摘要： Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.
摘要翻译：通过重排序操作和以特殊方式组织存储器分配，减少用于数字信号处理操作的存储器存储要求，例如，产生中间输出数据的运动补偿视频扫描速率转换，其被用作操作的输入以允许在特定执行时间的中间输出基本上共享与先前执行时间的中间输出相同的存储空间。这种减少处理操作所需的存储量有利地降低了成本和功耗。

3. 发明申请

US20100050052A1 PIPELINED ERROR DETERMINATION IN AN ERROR-CORRECTING COMMUNICATION SYSTEM 有权
标题翻译：错误校正通信系统中的管道错误确定
公开(公告)号：US20100050052A1
公开(公告)日：2010-02-25
申请号：US12556439
申请日：2009-09-09
申请人： Shaori Guo
发明人： Shaori Guo
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0052 , H04L1/0057 , H04L1/0061 , H04L1/0071
摘要： A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.
摘要翻译：在集成电路设备内接收数据分组序列并存储在其第一个存储器中。基于与数据分组序列相关联的错误信息，在集成电路设备的第二存储器内更新错误描述符值。每个错误描述符值包括指定第一存储器的对应存储区域的地址字段和指定存储在存储区域内的数据值的错误状态的错误字段。至少部分地基于错误描述符值的各个子集内的错误字段和地址字段生成多位错误值的序列。同时产生多位错误值中的至少一个，基于先前生成的多位错误值之一来改变存储在第一存储器中的数据值的一个或多个位的状态。

4. 发明授权

US07610544B2 Erasure generation in a forward-error-correcting communication system 有权
标题翻译：前向纠错通信系统中的擦除生成
公开(公告)号：US07610544B2
公开(公告)日：2009-10-27
申请号：US11437282
申请日：2006-05-18
申请人： Shaori Guo
发明人： Shaori Guo
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H04L1/0057 , H04L1/0061 , H04L1/0071
摘要： A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.
摘要翻译：在集成电路设备内接收第一数据分组，并且在由第一地址开始的第一存储器内存储第一数据分组，该第一地址由一个或多个先前接收到的数据分组的大小确定。错误描述符值在集成电路设备的第二存储器内被更新，错误描述符包括指示与第一数据包相关联的错误的错误字段，指示第一存储器内的第一地址的地址字段和长度字段，指示应用错误的存储位置的范围。至少部分地基于错误描述符生成多位错误值，所述多位错误值的每个位对应于第一存储器的存储行内的相应存储位置。至少部分地基于多位错误值来改变第一存储器的存储行内的一个或多个位的状态。

5. 发明授权

US08797835B1 Method and apparatus for detecting crosstalk between a plurality of devices communicating in accordance with a universal serial bus (USB) protocol 有权
标题翻译：用于检测根据通用串行总线（USB）协议通信的多个设备之间的串扰的方法和装置
公开(公告)号：US08797835B1
公开(公告)日：2014-08-05
申请号：US13593875
申请日：2012-08-24
申请人： Zhenyu Zhang , Dongxin Zhou , Baolei Xie , Shaori Guo , Jeanne Q. Cai , Eric Hung
发明人： Zhenyu Zhang , Dongxin Zhou , Baolei Xie , Shaori Guo , Jeanne Q. Cai , Eric Hung
IPC分类号： H04J1/12 , H04B3/46 , H04B3/32 , H04M3/34 , H04L5/14
CPC分类号： H04B3/464 , H04B3/32 , H04B3/487 , H04L5/1461 , H04M3/34
摘要： A first device comprising a transceiver module configured to begin transmission of a first signal to a second device. A control module is configured to, in response to the transceiver module receiving a second signal during the transmission of the first signal to the second device, determine whether the second signal corresponds to crosstalk by having the transceiver module suspend the transmission of the first signal. In response to the transceiver module continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does not correspond to crosstalk. In response to the transceiver module not continuing to receive the second signal subsequent to the transceiver module having suspended the transmission of the first signal to the second device, the control module determines that the second signal does correspond to crosstalk.
摘要翻译：第一设备，包括被配置为开始向第二设备发送第一信号的收发器模块。控制模块被配置为响应于收发器模块在向第二设备发送第一信号期间接收第二信号，通过使收发器模块暂停第一信号的传输来确定第二信号是否对应于串扰。响应于收发器模块在收发器模块已经暂停第一信号的传输到第二设备之后继续接收第二信号，则控制模块确定第二信号不对应于串扰。响应于收发器模块不继续接收收发器模块之后的第二信号，该第二信号暂停了第一信号的传输到第二设备，则控制模块确定第二信号确实对应于串扰。

6. 发明申请

US20120320966A1 ADAPTIVE VIDEO DECODING CIRCUITRY AND TECHNIQUES 审中-公开
标题翻译：自适应视频解码电路和技术
公开(公告)号：US20120320966A1
公开(公告)日：2012-12-20
申请号：US13143047
申请日：2011-02-14
申请人： Shaori Guo , Zubing Yuan , Jun Ding
发明人： Shaori Guo , Zubing Yuan , Jun Ding
IPC分类号： H04N7/32 , H04N7/26
CPC分类号： H04N5/46 , H04N19/102 , H04N19/159 , H04N19/177 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/4382 , H04N21/44008 , H04N21/440263 , H04N21/440281
摘要： A method and circuitry for decoding an encoded video data stream which corresponds to a selected channel which is one of a plurality of channels of a broadcast spectrum. In one aspect, the method comprises determining one or more characteristics of the encoded video data stream, decoding the encoded video data stream to generate video data, wherein: (i) in response to determining the encoded video data stream includes a first characteristic, the encoded video data stream is decoded using a first decoding mode wherein, in response to decoding the encoded video data stream using the first decoding mode, the video data includes a first spatial resolution and a first temporal resolution, and (ii) in response to determining the encoded video data stream includes a second characteristic, the encoded video data stream is decoded using a second decoding mode wherein, in response to decoding the encoded video data stream using the second decoding mode, the video data includes a second spatial resolution and a second temporal resolution, wherein the first spatial resolution is different from the second spatial resolution and/or the first temporal resolution is different from the second temporal resolution.
摘要翻译：一种用于解码对应于作为广播频谱的多个频道之一的所选频道的编码视频数据流的方法和电路。一方面，该方法包括确定编码视频数据流的一个或多个特性，解码编码视频数据流以产生视频数据，其中：（i）响应于确定编码视频数据流包括第一特征，使用第一解码模式解码编码视频数据流，其中响应于使用第一解码模式解码编码视频数据流，视频数据包括第一空间分辨率和第一时间分辨率，以及（ii）响应于确定编码视频数据流包括第二特性，使用第二解码模式解码编码视频数据流，其中响应于使用第二解码模式解码编码视频数据流，视频数据包括第二空间分辨率和第二解码模式时间分辨率，其中第一空间分辨率不同于第二空间分辨率和/或第一时间分辨率是d 不同于第二时间分辨率。

7. 发明申请

US20060282749A1 Erasure generation in a forward-error-correcting communication system 有权
公开(公告)号：US20060282749A1
公开(公告)日：2006-12-14
申请号：US11437282
申请日：2006-05-18
申请人： Shaori Guo
发明人： Shaori Guo
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H04L1/0057 , H04L1/0061 , H04L1/0071
摘要： A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.

8. 发明授权

US08891022B2 Fast-booting broadcast television receiver 有权
标题翻译：快速启动广播电视接收机
公开(公告)号：US08891022B2
公开(公告)日：2014-11-18
申请号：US12853085
申请日：2010-08-09
申请人： Shaori Guo , Zu Bing Yuan , Andrew J. Burstein
发明人： Shaori Guo , Zu Bing Yuan , Andrew J. Burstein
IPC分类号： H04N7/14 , H04N21/443
CPC分类号： H04N21/4432
摘要： Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.
摘要翻译：通过将操作程序的一部分加载到电视接收机IC中，可以大大减少电视接收机IC内的启动延迟，以便能够执行耗时的接收机初始化操作，然后在加载接收机初始化操作的同时执行接收机初始化操作操作程序进入电视接收机IC。通过该操作，执行接收机初始化操作所需的时间可以在加载操作程序所需的时间内至少部分地隐藏，从而大大减少启动延迟。

9. 发明授权

US08301949B2 Pipelined error determination in an error-correcting communication system 有权
标题翻译：错误纠正通信系统中的流水线错误确定
公开(公告)号：US08301949B2
公开(公告)日：2012-10-30
申请号：US12556439
申请日：2009-09-09
申请人： Shaori Guo
发明人： Shaori Guo
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H04L1/0057 , H04L1/0061 , H04L1/0071
摘要： A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.
摘要翻译：在集成电路设备内接收数据分组序列并存储在其第一个存储器中。基于与数据分组序列相关联的错误信息，在集成电路设备的第二存储器内更新错误描述符值。每个错误描述符值包括指定第一存储器的对应存储区域的地址字段和指定存储在存储区域内的数据值的错误状态的错误字段。至少部分地基于错误描述符值的各个子集内的错误字段和地址字段生成多位错误值的序列。同时产生多位错误值中的至少一个，存储在第一存储器中的数据值的一个或多个位的状态基于先前生成的多位错误值之一而改变。

10. 发明授权

US08115874B2 Memory optimization for video processing 有权
标题翻译：视频处理的内存优化
公开(公告)号：US08115874B2
公开(公告)日：2012-02-14
申请号：US11575487
申请日：2005-09-16
申请人： Shaori Guo , Selliah Rathnam , Gwo Giun Lee
发明人： Shaori Guo , Selliah Rathnam , Gwo Giun Lee
IPC分类号： H04N9/64
CPC分类号： H04N19/426 , H04N7/014 , H04N19/433
摘要： Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.
摘要翻译：通过重排序操作和以特殊方式组织存储器分配，减少用于数字信号处理操作的存储器存储要求，例如，产生中间输出数据的运动补偿视频扫描速率转换，其被用作操作的输入以允许在特定执行时间的中间输出基本上共享与先前执行时间的中间输出相同的存储空间。这种减少处理操作所需的存储量有利地降低了成本和功耗。

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