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1. 发明授权

US06849541B1 Method of fabricating a dual damascene copper wire 有权
标题翻译：制造双镶嵌铜线的方法
公开(公告)号：US06849541B1
公开(公告)日：2005-02-01
申请号：US10707517
申请日：2003-12-19
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang , Tzung-Yu Hung
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang , Tzung-Yu Hung
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76811 , H01L21/76813 , H01L21/76831 , H01L21/76873 , H01L2221/1089
摘要： A method of forming at least one wire on a substrate. The substrate includes at least one conductive region. An insulating layer is disposed on the substrate. At least one recess in the insulating layer exposes the conductive region. A barrier layer is formed on a surface of the insulating layer and the recess first. A continuous and uniform conductive layer is then formed on a surface of the barrier layer. A seed layer is thereafter formed on a surface of the conductive layer. Finally, a metal layer filling up the recess is formed on a surface of the seed layer.
摘要翻译：一种在衬底上形成至少一根线的方法。衬底包括至少一个导电区域。绝缘层设置在基板上。绝缘层中的至少一个凹部露出导电区域。首先在绝缘层的表面和凹部上形成阻挡层。然后在阻挡层的表面上形成连续且均匀的导电层。此后在导电层的表面上形成晶种层。最后，在种子层的表面上形成填充凹部的金属层。

2. 发明申请

US20050098892A1 Structure and process of metal interconnects 审中-公开
标题翻译：金属互连的结构和工艺
公开(公告)号：US20050098892A1
公开(公告)日：2005-05-12
申请号：US10718897
申请日：2003-11-20
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.
摘要翻译：提供金属互连的工艺和由其制造的金属互连结构。在电介质层中形成开口。在填充开口的电介质层上形成金属层。在金属层和电介质层上形成膜层。在热处理期间，膜层与金属层反应，在金属层的表面形成保护层。除去与金属层不反应的膜层的部分，以避免金属层之间的短路。保护层可以保护金属层的表面免受氧化，从而可以有效地促进半导体器件的稳定性和可靠性。

3. 发明授权

US07397124B2 Process of metal interconnects 有权
标题翻译：金属互连工艺
公开(公告)号：US07397124B2
公开(公告)日：2008-07-08
申请号：US11155729
申请日：2005-06-16
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.
摘要翻译：提供金属互连的工艺和由其制造的金属互连结构。在电介质层中形成开口。在填充开口的电介质层上形成金属层。在金属层和电介质层上形成膜层。在热处理期间，膜层与金属层反应，在金属层的表面形成保护层。除去与金属层不反应的膜层的部分，以避免金属层之间的短路。保护层可以保护金属层的表面免受氧化，从而可以有效地促进半导体器件的稳定性和可靠性。

4. 发明申请

US20050250312A1 Structure and process of metal interconnects 有权
公开(公告)号：US20050250312A1
公开(公告)日：2005-11-10
申请号：US11155729
申请日：2005-06-16
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

5. 发明申请

US20070105367A1 Method for forming barrier layer 有权
标题翻译：形成阻挡层的方法
公开(公告)号：US20070105367A1
公开(公告)日：2007-05-10
申请号：US11646387
申请日：2006-12-28
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855 , H01L21/76846 , H01L21/76862
摘要： A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：形成阻挡层的方法包括以下步骤：提供导电层，在导电层上形成第一介电层，第一介电层在其中具有通孔，形成覆盖第一介电层和导电层的第一金属层，形成在第一金属层上的金属化材料层，去除第一介电层中的通孔底部上方的金属化材料层，并将金属化材料层留在第一介电层中的通孔的侧壁上; 以及形成覆盖所述金属化材料层的第二金属层。完成的阻挡层在第一介电层的底部通孔中将具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

6. 发明授权

US08587128B2 Damascene structure 有权
标题翻译：大马士革结构
公开(公告)号：US08587128B2
公开(公告)日：2013-11-19
申请号：US13397833
申请日：2012-02-16
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76844 , H01L21/76846
摘要： A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：镶嵌结构包括依次形成在导电层上的导电层，第一介电层，第一阻挡金属层，阻挡层和第二阻挡金属层。第一电介质层中具有通孔。阻挡层由与第一阻挡金属层不同的材料构成。设置在通孔底部上的阻挡层的底部不穿孔。完成的阻挡层在第一介电层中的通孔底部具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

7. 发明授权

US07645698B2 Method for forming barrier layer 有权
标题翻译：形成阻挡层的方法
公开(公告)号：US07645698B2
公开(公告)日：2010-01-12
申请号：US11646387
申请日：2006-12-28
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855 , H01L21/76846 , H01L21/76862
摘要： A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：形成阻挡层的方法包括以下步骤：提供导电层，在导电层上形成第一介电层，第一介电层在其中具有通孔，形成覆盖第一介电层和导电层的第一金属层，形成在第一金属层上的金属化材料层，去除第一介电层中的通孔底部上方的金属化材料层，并将金属化材料层留在第一介电层中的通孔的侧壁上; 以及形成覆盖所述金属化材料层的第二金属层。完成的阻挡层在第一介电层的底部通孔中将具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

8. 发明授权

US07199040B2 Barrier layer structure 有权
标题翻译：阻隔层结构
公开(公告)号：US07199040B2
公开(公告)日：2007-04-03
申请号：US10841562
申请日：2004-05-10
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76844 , H01L21/2855 , H01L21/76846 , H01L21/76862
摘要： A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：阻挡层结构包括在导电层上形成的第一介电层，并且在第一介电层中形成通孔，其中第一介电层中的通孔连接到导电层。第一金属层被阶梯式地覆盖在第一介电层上。金属化材料层被阶梯式地覆盖在第一金属层上，但是金属化材料层不覆盖连接到电介质层中的导电层的通孔底部上的第一金属层。第二金属层被阶梯式地覆盖在金属化材料层上，并且第二金属层覆盖连接到电介质层中的导电层的通孔底部上的第一金属层。阻挡层结构在第一电介质层的底部通孔中具有较低的电阻率，并且能够防止铜原子扩散到电介质层中。

9. 发明授权

US08766319B2 Semiconductor device with ultra thin silicide layer 有权
标题翻译：具有超薄硅化物层的半导体器件
公开(公告)号：US08766319B2
公开(公告)日：2014-07-01
申请号：US13456238
申请日：2012-04-26
申请人： Kuo-Chih Lai , Chia Chang Hsu , Nien-Ting Ho , Bor-Shyang Liao , Shu Min Huang , Min-Chung Cheng , Yu-Ru Yang
发明人： Kuo-Chih Lai , Chia Chang Hsu , Nien-Ting Ho , Bor-Shyang Liao , Shu Min Huang , Min-Chung Cheng , Yu-Ru Yang
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/76889 , H01L29/41791 , H01L29/66795
摘要： A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
摘要翻译：半导体器件的制造方法包括以下步骤。首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。然后在去除金属层之后执行RTP。

10. 发明授权

US08310012B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08310012B2
公开(公告)日：2012-11-13
申请号：US12759670
申请日：2010-04-13
申请人： Guang-Yaw Hwang , Yu-Ru Yang , Jiunn-Hsiung Liao , Pei-Yu Chou
发明人： Guang-Yaw Hwang , Yu-Ru Yang , Jiunn-Hsiung Liao , Pei-Yu Chou
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/82385 , H01L29/42372 , H01L29/4966 , H01L29/66545 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的栅极电介质层和形成在栅极介电层上的至少第一导电型金属栅极。第一导电型金属栅极包括在填充金属层和栅极介电层之间形成的填充金属层和U型金属层。 U型金属层的最上部比填充金属层低。

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