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1. 发明授权

US06775756B1 Method and apparatus for out of order memory processing within an in order processor 有权
标题翻译：用于在订单处理器内进行无序存储处理的方法和装置
公开(公告)号：US06775756B1
公开(公告)日：2004-08-10
申请号：US09416196
申请日：1999-10-11
申请人： Shalesh Thusoo , Niteen Patkar , Jim Lin
发明人： Shalesh Thusoo , Niteen Patkar , Jim Lin
IPC分类号： G06F1200
CPC分类号： G06F9/3834
摘要： A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.
摘要翻译：用于按顺序处理设备中的无序存储器处理的方法和装置包括允许以流水线方式处理多个存储器事务的处理，直到在两个或多个存储器事务之间产生依赖性。对于多个存储器事务中的每一个，这种处理包括确定与事务相关联的数据是否被存储在本地高速缓存中。如果数据存储在本地缓存中，则在下一个流水线间隔中将其写入数据寄存器。当与存储器事务相关联的数据未存储在本地高速缓存中时，通过将存储器事务存储在未命中缓冲器中来继续处理。当接收到数据而不考虑流水线方式时，将识别在缺失缓冲器中的存储器事务的相关数据写入数据寄存器，继续进行处理。

2. 发明授权

US06389519B1 Method and apparatus for providing probe based bus locking and address locking 有权
标题翻译：用于提供基于探头的总线锁定和地址锁定的方法和装置
公开(公告)号：US06389519B1
公开(公告)日：2002-05-14
申请号：US09356732
申请日：1999-07-19
申请人： Shalesh Thusoo , Niteen Patkar
发明人： Shalesh Thusoo , Niteen Patkar
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.
摘要翻译：用于通过多个数据处理器有助于通过公共总线访问共享存储器地址的方法和装置包括至少由第一处理器检测两个存取地址是地址边界两边的边界地址。响应于检测到两个访问地址，该方法和装置锁定公共总线。此外，该方法和装置基于由第一处理器传送的地址探测查询数据来锁定两个检测到的地址。因此，至少一个处理器使用基于探针的总线锁定和地址锁定控制来促进对共享存储器地址的有效访问。优选地，每个处理器包括基于探针的总线锁定和地址锁定控制。该方法和装置在需要时提供一种具有确定性总线锁定的地址锁定。

3. 发明授权

US06643726B1 Method of manufacture and apparatus of an integrated computing system 有权
标题翻译：集成计算系统的制造方法和装置
公开(公告)号：US06643726B1
公开(公告)日：2003-11-04
申请号：US09376820
申请日：1999-08-18
申请人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
发明人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
IPC分类号： G06F1336
CPC分类号： G06F13/368
摘要： An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.
摘要翻译：集成计算系统包括形成在衬底上的至少一个处理器，其中处理器以处理器速率工作。集成计算系统还包括耦合到至少一个处理器并形成在基板上的全局总线。全局总线以等于或大于处理速率的速率支持事务（例如，数据，操作指令和/或控制信令传送）。集成计算系统还包括可操作地耦合到全局总线并形成在基板上的设备网关和存储器网关。设备网关为全局总线的至少一个设备（例如，内部或外部）提供接口。存储器网关提供全局总线和存储器之间的接口。

4. 发明授权

US06430646B1 Method and apparatus for interfacing a processor with a bus 有权
标题翻译：处理器与总线接口的方法和装置
公开(公告)号：US06430646B1
公开(公告)日：2002-08-06
申请号：US09377004
申请日：1999-08-18
申请人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
发明人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.
摘要翻译：一种用于将处理器与总线接口的方法和装置包括通过将由处理器发起的事务存储到缓冲器中而开始的处理。然后，通过选择存储在缓冲器中的一个事务并将所选择的事务放置在总线上来继续处理。通过监视缓冲区中每个事务的执行进度并在事务成功完成时标记事务，继续进行处理。处理还包括在从缓冲器中选择一个事务之前处理至少两个相关事务，其中如果可以在本地处理事务，则它们不需要在总线上传输。此外，该处理包括监视由另一处理器发起的相关事务的总线，使得可以更有效地处理这些事务。总线上的相关事务将对应于在缓冲器中排队的事务。

5. 发明授权

US06578134B1 Multi-branch resolution 失效
标题翻译：多分支分辨率
公开(公告)号：US06578134B1
公开(公告)日：2003-06-10
申请号：US09451300
申请日：1999-11-29
申请人： Korbin Van Dyke , Niteen Patkar , Shalesh Thusoo , TR Ramesh
发明人： Korbin Van Dyke , Niteen Patkar , Shalesh Thusoo , TR Ramesh
IPC分类号： G06F938
CPC分类号： G06F9/30094 , G06F9/3844 , G06F9/3867
摘要： A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.
摘要翻译：提供了一种用于按顺序处理器的分支分辨率逻辑，其扫描处理器流水线的阶段以确定具有足够的用于分辨率的条件代码的最旧分支指令。这些阶段从后面的阶段到早期的阶段进行扫描，这样可以快速和简单的分支分辨率。因此，由于分支在特定阶段产生必要条件代码后立即得到解决，所以分支误判处罚最小化。

6. 发明授权

US07240255B2 Area efficient BIST system for memories 有权
标题翻译：区域高效BIST系统用于记忆
公开(公告)号：US07240255B2
公开(公告)日：2007-07-03
申请号：US11088636
申请日：2005-03-22
申请人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
发明人： Charles Akum Njinda , Shalesh Thusoo , Hao Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/26 , G11C29/56012 , G11C2029/0401 , G11C2029/4402 , G11C2029/5602
摘要： A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.
摘要翻译：具有用于IC的单个BIST的系统，其包括可能具有不同延迟，宽度和深度的多个存储器阵列。串行总线（可能是调试总线）连接BIST控制器，IC上的每个存储器阵列和控制器。每个存储器阵列具有关联的测试辅助逻辑（DAL）模块。与任何特定存储器阵列相关联的DAL识别来自用于相关联存储器阵列的BIST的命令，控制相关阵列的写入/读取命令的执行，并且在存储器阵列中读取的数据与适当的命令一起发送到比较器适用于相关阵列的延迟因此，有BIST的标准化命令，但是每个DAL以适合与特定DAL相关联的存储器阵列（或阵列）的方式执行这些命令。

7. 发明授权

US5687336A Stack push/pop tracking and pairing in a pipelined processor 失效
标题翻译：在流水线处理器中堆栈推/弹跟踪和配对
公开(公告)号：US5687336A
公开(公告)日：1997-11-11
申请号：US584836
申请日：1996-01-11
申请人： Gene Shen , Shalesh Thusoo , James S. Blomgren
发明人： Gene Shen , Shalesh Thusoo , James S. Blomgren
IPC分类号： G06F9/34 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3816 , G06F9/34 , G06F9/3824
摘要： A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack pointer is needed for generating the stack-top address in memory. The stack-top address is generated early in the pipeline. Other stack instructions in the pipeline which have not yet incremented the stack pointer are located with a stack valid bit array. The stack valid array indicates the increment or decrement amounts for stack instructions in each pipeline stage. An overall displacement or increment value is computed as the sum of all increments and decrements for stack instructions in the pipeline which have not yet updated the stack pointer. The overall displacement which accounts for all unfinished stack instructions is added to the stack pointer from the register file to generate the stack-top address. Thus the new stack pointer does not have to be generated before the stack memory is accessed. Pushes or pops are paired by doubling the increment amount in the stack valid bit array and performing a double-width data transfer.
摘要翻译：流水线处理器同时执行多个堆栈指令。不需要额外的影子寄存器用于管道中指令的堆栈指针。相反，新的堆栈指针在流水线的末尾生成一次并写入寄存器文件。需要堆栈指针来生成内存中的堆栈顶部地址。栈顶地址在管道中提前生成。流水线中尚未增加堆栈指针的其他堆栈指令位于堆栈有效位数组中。堆栈有效数组表示每个流水线阶段堆栈指令的增量或减量量。总体位移或增量值被计算为流水线中尚未更新堆栈指针的堆栈指令的所有增量和减量的总和。考虑到所有未完成的堆栈指令的总体位移从寄存器文件添加到堆栈指针以生成堆栈顶部地址。因此，在访问堆栈内存之前，不必生成新的堆栈指针。通过将堆栈有效位数组中的增量量加倍并执行双宽度数据传输，推送或弹出配对。

8. 发明授权

US07013456B1 Profiling execution of computer programs 有权
标题翻译：分析计算机程序的执行情况
公开(公告)号：US07013456B1
公开(公告)日：2006-03-14
申请号：US09334530
申请日：1999-06-16
申请人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
发明人： Korbin S. Van Dyke , Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Stephen C. Purcell , Niteen Aravind Patkar
IPC分类号： G06F9/44
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/45554
摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.
摘要翻译：一种用于执行该方法的方法和计算机。在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

9. 发明申请

US20060218452A1 Area efficient BIST system for memories 有权
标题翻译：区域高效BIST系统用于记忆
公开(公告)号：US20060218452A1
公开(公告)日：2006-09-28
申请号：US11088636
申请日：2005-03-22
申请人： Charles Njinda , Shalesh Thusoo , Hao Wang
发明人： Charles Njinda , Shalesh Thusoo , Hao Wang
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/14 , G11C29/26 , G11C29/56012 , G11C2029/0401 , G11C2029/4402 , G11C2029/5602
摘要： A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with he particular DAL.
摘要翻译：具有用于IC的单个BIST的系统，其包括可能具有不同延迟，宽度和深度的多个存储器阵列。串行总线（可能是调试总线）连接BIST控制器，IC上的每个存储器阵列和控制器。每个存储器阵列具有关联的测试辅助逻辑（DAL）模块。与任何特定存储器阵列相关联的DAL识别来自用于相关联存储器阵列的BIST的命令，控制相关阵列的写入/读取命令的执行，并且在存储器阵列中读取的数据与适当的命令一起发送到比较器延迟适用于相关联的阵列因此，有来自BIST的标准化命令，但每个DAL以适合与特定DAL相关联的存储器阵列（或阵列）的方式执行这些命令。

10. 发明授权

US06826748B1 Profiling program execution into registers of a computer 有权
标题翻译：将程序执行分析到计算机的寄存器中
公开(公告)号：US06826748B1
公开(公告)日：2004-11-30
申请号：US09339749
申请日：1999-06-24
申请人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
发明人： Paul H. Hohensee , David L. Reese , John S. Yates, Jr. , Korbin S. Van Dyke , T. R. Ramesh , Shalesh Thusoo , Gurjeet Singh Saund , Niteen Aravind Patkar
IPC分类号： G06F944
CPC分类号： G06F9/45558 , G06F9/45541 , G06F9/45554 , G06F2009/45583
摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.
摘要翻译：用于执行该方法的方法和计算机。在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

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