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1. 发明授权

US06643726B1 Method of manufacture and apparatus of an integrated computing system 有权
标题翻译：集成计算系统的制造方法和装置
公开(公告)号：US06643726B1
公开(公告)日：2003-11-04
申请号：US09376820
申请日：1999-08-18
申请人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
发明人： Niteen Patkar , Ali Alasti , Don Van Dyke , Korbin Van Dyke , Shalesh Thusoo , Stephen C. Purcell , Govind Malalur
IPC分类号： G06F1336
CPC分类号： G06F13/368
摘要： An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.
摘要翻译：集成计算系统包括形成在衬底上的至少一个处理器，其中处理器以处理器速率工作。集成计算系统还包括耦合到至少一个处理器并形成在基板上的全局总线。全局总线以等于或大于处理速率的速率支持事务（例如，数据，操作指令和/或控制信令传送）。集成计算系统还包括可操作地耦合到全局总线并形成在基板上的设备网关和存储器网关。设备网关为全局总线的至少一个设备（例如，内部或外部）提供接口。存储器网关提供全局总线和存储器之间的接口。

2. 发明授权

US06430646B1 Method and apparatus for interfacing a processor with a bus 有权
标题翻译：处理器与总线接口的方法和装置
公开(公告)号：US06430646B1
公开(公告)日：2002-08-06
申请号：US09377004
申请日：1999-08-18
申请人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
发明人： Shalesh Thusoo , Niteen Patkar , Korbin Van Dyke , Stephen C. Purcell
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.
摘要翻译：一种用于将处理器与总线接口的方法和装置包括通过将由处理器发起的事务存储到缓冲器中而开始的处理。然后，通过选择存储在缓冲器中的一个事务并将所选择的事务放置在总线上来继续处理。通过监视缓冲区中每个事务的执行进度并在事务成功完成时标记事务，继续进行处理。处理还包括在从缓冲器中选择一个事务之前处理至少两个相关事务，其中如果可以在本地处理事务，则它们不需要在总线上传输。此外，该处理包括监视由另一处理器发起的相关事务的总线，使得可以更有效地处理这些事务。总线上的相关事务将对应于在缓冲器中排队的事务。

3. 发明授权

US06578134B1 Multi-branch resolution 失效
标题翻译：多分支分辨率
公开(公告)号：US06578134B1
公开(公告)日：2003-06-10
申请号：US09451300
申请日：1999-11-29
申请人： Korbin Van Dyke , Niteen Patkar , Shalesh Thusoo , TR Ramesh
发明人： Korbin Van Dyke , Niteen Patkar , Shalesh Thusoo , TR Ramesh
IPC分类号： G06F938
CPC分类号： G06F9/30094 , G06F9/3844 , G06F9/3867
摘要： A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.
摘要翻译：提供了一种用于按顺序处理器的分支分辨率逻辑，其扫描处理器流水线的阶段以确定具有足够的用于分辨率的条件代码的最旧分支指令。这些阶段从后面的阶段到早期的阶段进行扫描，这样可以快速和简单的分支分辨率。因此，由于分支在特定阶段产生必要条件代码后立即得到解决，所以分支误判处罚最小化。

4. 发明授权

US06745318B1 Method and apparatus of configurable processing 有权
标题翻译：可配置处理的方法和装置
公开(公告)号：US06745318B1
公开(公告)日：2004-06-01
申请号：US09376830
申请日：1999-08-18
申请人： Sanjay Mansingh , Niteen Patkar , Korbin Van Dyke , Stephen Hale , Dee Tovey , Nital Patwa , Stephen C. Purcell
发明人： Sanjay Mansingh , Niteen Patkar , Korbin Van Dyke , Stephen Hale , Dee Tovey , Nital Patwa , Stephen C. Purcell
IPC分类号： G06F1710
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/3897
摘要： An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.
摘要翻译：提供可配置处理的装置包括取出模块，解码器和动态运算单元。提取模块可操作以获取至少一个指令并将其提供给解码器。解码器接收指令并对其进行解码。动态算术逻辑单元接收解码指令，并配置至少一个可配置的算术逻辑单元，以执行解码指令中包含的操作。

5. 发明授权

US06775756B1 Method and apparatus for out of order memory processing within an in order processor 有权
标题翻译：用于在订单处理器内进行无序存储处理的方法和装置
公开(公告)号：US06775756B1
公开(公告)日：2004-08-10
申请号：US09416196
申请日：1999-10-11
申请人： Shalesh Thusoo , Niteen Patkar , Jim Lin
发明人： Shalesh Thusoo , Niteen Patkar , Jim Lin
IPC分类号： G06F1200
CPC分类号： G06F9/3834
摘要： A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.
摘要翻译：用于按顺序处理设备中的无序存储器处理的方法和装置包括允许以流水线方式处理多个存储器事务的处理，直到在两个或多个存储器事务之间产生依赖性。对于多个存储器事务中的每一个，这种处理包括确定与事务相关联的数据是否被存储在本地高速缓存中。如果数据存储在本地缓存中，则在下一个流水线间隔中将其写入数据寄存器。当与存储器事务相关联的数据未存储在本地高速缓存中时，通过将存储器事务存储在未命中缓冲器中来继续处理。当接收到数据而不考虑流水线方式时，将识别在缺失缓冲器中的存储器事务的相关数据写入数据寄存器，继续进行处理。

6. 发明授权

US06389519B1 Method and apparatus for providing probe based bus locking and address locking 有权
标题翻译：用于提供基于探头的总线锁定和地址锁定的方法和装置
公开(公告)号：US06389519B1
公开(公告)日：2002-05-14
申请号：US09356732
申请日：1999-07-19
申请人： Shalesh Thusoo , Niteen Patkar
发明人： Shalesh Thusoo , Niteen Patkar
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.
摘要翻译：用于通过多个数据处理器有助于通过公共总线访问共享存储器地址的方法和装置包括至少由第一处理器检测两个存取地址是地址边界两边的边界地址。响应于检测到两个访问地址，该方法和装置锁定公共总线。此外，该方法和装置基于由第一处理器传送的地址探测查询数据来锁定两个检测到的地址。因此，至少一个处理器使用基于探针的总线锁定和地址锁定控制来促进对共享存储器地址的有效访问。优选地，每个处理器包括基于探针的总线锁定和地址锁定控制。该方法和装置在需要时提供一种具有确定性总线锁定的地址锁定。

7. 发明授权

US06701426B1 Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets 有权
标题翻译：基于哪个指令集可操作的多个分支预测处理之间切换，其中分支历史数据结构对于多个指令集是相同的
公开(公告)号：US06701426B1
公开(公告)日：2004-03-02
申请号：US09425037
申请日：1999-10-19
申请人： Greg L. Ries , Ronak S. Patel , Korbin S. Van Dyke , Niteen Patkar , T. R. Ramesh
发明人： Greg L. Ries , Ronak S. Patel , Korbin S. Van Dyke , Niteen Patkar , T. R. Ramesh
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/30174 , G06F9/3848
摘要： A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.
摘要翻译：多指令集处理器和方法根据多指令集中的哪一个可操作地动态地激活多个分支预测处理中的一个。使用共享分支历史表结构，并根据哪个指令集可操作而进行索引。该装置和方法还允许在指令集索引生成器之间切换多个指令集中的每一个。因此，取决于多个指令集中的哪一个是可操作的，使用不同的分支预测数据索引。响应于指令集的选择，可以使用共享存储器来包含来自多个指令集中的每一个的指令的分支预测表数据。响应于选择一个指令集，共享存储器还用于包含来自多个指令集中的每一个的指令的转移目标缓冲器数据。

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