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1. 发明授权

US5778219A Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效
标题翻译：在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译：支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。如果推测操作使用产生异常的推测操作的结果，则会传播该异常。使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。要检查延迟异常，功能单元然后读取寄存器文件。如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。

2. 发明授权

US5692169A Method and system for deferring exceptions generated during speculative execution 失效
标题翻译：用于推迟在投机执行期间产生的异常的方法和系统
公开(公告)号：US5692169A
公开(公告)日：1997-11-25
申请号：US324940
申请日：1994-10-18
申请人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
发明人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
IPC分类号： G06F9/318 , G06F9/38 , G06F9/45 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/30189 , G06F9/3842
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.
摘要翻译：支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。如果推测操作使用产生异常的推测操作的结果，则会传播该异常。使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。要检查延迟异常，功能单元然后读取寄存器文件。

3. 发明授权

US5721865A Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory 失效
标题翻译：具有预取控制的信息处理装置，用于通过高速缓冲存储器从存储器预取数据结构
公开(公告)号：US5721865A
公开(公告)日：1998-02-24
申请号：US588503
申请日：1996-01-18
申请人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
发明人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
IPC分类号： G06F9/345 , G06F9/38 , G06F12/02 , G06F12/08 , G06F17/16 , G06F9/34
CPC分类号： G06F9/3455 , G06F9/30047 , G06F9/30181 , G06F9/383 , G06F9/3834
摘要： To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.
摘要翻译：为了改进用于预取由处理器访问的数据的电路的功能，预取单元在其中结合有用于发出读取需要预取的一组数据的请求的电路，并且用于保存响应于读取读取的数据组的寄存器请求。在高速缓存请求单元的控制下，从高速缓冲存储器或主存储器读出数据组。可以预取多组数据。当进行数据指定时，处理器请求高速缓冲存储器读取要预取的数据所属的块。预取单元中还包括一个电路，其中当处理器随后更新预取的数据时，其更新的数据变为无效。也可以读出结构中的向量复合体的元素，例如索引向量等。也可以处理处理器内产生的中断。

4. 发明授权

US5475823A Memory processor that prevents errors when load instructions are moved in the execution sequence 失效
标题翻译：内存处理器可以在执行顺序中移动加载指令时防止错误
公开(公告)号：US5475823A
公开(公告)日：1995-12-12
申请号：US261647
申请日：1994-06-17
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , Michael S. Schlansker
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , Michael S. Schlansker
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/45 , G06F12/00 , G06F9/00
CPC分类号： G06F9/30043 , G06F9/3834
摘要： A memory processor which prevents errors when the compiler advances long latency load instructions in the instruction sequence to reduce the loss of efficiency resulting from the latency time. The memory processor intercepts all load and store instructions prior to the instructions entering the memory pipeline. The memory processor stores load instructions for a period of time sufficient to determine if any subsequent store instruction that would have been executed prior to the load instruction, had the load instruction not been moved, references the same address as that specified in the load instruction. If a store instruction references the load instruction address, the invention returns the same data as the load instruction would have if it was not moved by the compiler.
摘要翻译：一种存储器处理器，当编译器在指令序列中前进长延迟加载指令时，可以防止错误，以减少延迟时间导致的效率损失。存储器处理器在指令进入存储器管线之前拦截所有的加载和存储指令。存储器处理器将加载指令存储一段时间，足以确定在加载指令之前已经执行的加载指令是否有任何后续存储指令，如果加载指令未被移动，则引用与加载指令中指定的地址相同的地址。如果存储指令引用加载指令地址，则本发明返回与加载指令不被编译器移动的数据相同的数据。

5. 发明授权

US5689653A Vector memory operations 失效
标题翻译：矢量内存操作
公开(公告)号：US5689653A
公开(公告)日：1997-11-18
申请号：US384308
申请日：1995-02-06
申请人： Alan H. Karp , Frederic C. Amerson , Dennis Brzezinski , Rajiv Gupta , William S. Worley, Jr.
发明人： Alan H. Karp , Frederic C. Amerson , Dennis Brzezinski , Rajiv Gupta , William S. Worley, Jr.
IPC分类号： G06F9/312 , G06F9/345 , G06F9/38 , G06F12/00 , G06F15/78 , G06F17/16 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30036 , G06F9/3455 , G06F9/383
摘要： The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
摘要翻译：通过提供一个或多个向量缓冲器来减轻计算机系统的操作码带宽限制。数据在存储器和处理器寄存器之间使用向量缓冲区在两部分进程中传输。在第一部分中，向量请求指令通过将数据存储在识别存储器中的一组数据元素（矢量）的控制寄存器中来发起数据的缓冲。当识别信息被加载到控制寄存器中时，向量预取控制器在存储器和向量缓冲器之间传送向量的元素。在第二部分中，向量元素操作指令将矢量的下一个元素传送到矢量缓冲器和指定的处理器寄存器之间，用于算术或逻辑运算。

6. 发明授权

US5615386A Computer architecture for reducing delays due to branch instructions 失效
标题翻译：用于减少分支指令导致的延迟的计算机体系结构
公开(公告)号：US5615386A
公开(公告)日：1997-03-25
申请号：US588151
申请日：1996-01-18
申请人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
发明人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.
摘要翻译：公开了一种用于执行具有较低等待时间并且很少需要刷新指令流水线的分支指令的改进的数据处理系统。数据处理系统利用寄存器文件来保存执行分支指令所需的信息。信息在分支指令之前被加载到寄存器文件中。这允许系统在任何给定时间准备多个分支指令。本发明可以用于使得包含分支指令的目标地址的高速缓存线在目标地址对于分支指令可用时很快被加载。由于分支指令的结果在分支指令进入指令流水线时几乎总是被知道，所以指令流水线很少需要刷新。

7. 发明授权

US5564031A Dynamic allocation of registers to procedures in a digital computer 失效
标题翻译：动态分配寄存器到数字计算机中的程序
公开(公告)号：US5564031A
公开(公告)日：1996-10-08
申请号：US629041
申请日：1996-04-12
申请人： Frederic C. Amerson , Robert M. English , Rajiv Gupta , Tan Watanabe
发明人： Frederic C. Amerson , Robert M. English , Rajiv Gupta , Tan Watanabe
IPC分类号： G06F9/42 , G06F7/72 , G06F9/30 , G06F9/46 , G06F9/48 , G06F12/06
CPC分类号： G06F9/462 , G06F7/72 , G06F9/30123 , G06F9/30134
摘要： In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to minimize main memory references. A called procedure dynamically allocates local registers as needed without regard to registers used by the caller of the procedure or by any callee of the procedure, whereby register allocation is not restricted by any predetermined window size. Local registers, including parameter passing registers, are allocated in the called procedure, rather than a priori at compile time, by adjusting register stack pointer values. Only the number of registers actually required by the procedure need by allocated. Optionally, rotating registers may be allocated among the local registers. Stack pointer values are stored in one of the parameter passing registers when a procedure is called. Hardware register file access circuitry maps virtual register numbers used by the procedures into the hardware register file. Upon return from a procedure, registers are deallocated by adjusting the register stack pointers to the values stored when the procedure was called.
摘要翻译：在数字计算机中，寄存器文件中的寄存器的循环队列被分配为用于过程的临时本地存储器，而不是使用已知的调用者/被调用者保存约定来最小化主存储器引用。被调用的过程根据需要动态地分配本地寄存器，而不考虑由过程的调用者使用的寄存器或过程的任何被调用者，由此寄存器分配不受任何预定窗口大小的限制。本地寄存器（包括参数传递寄存器）在调用过程中被分配，而不是在编译时通过调整寄存器堆栈指针值来先验地分配。只有实际需要的寄存器数量需要分配。可选地，可以在本地寄存器之间分配旋转寄存器。调用过程时，堆栈指针值存储在参数传递寄存器之一中。硬件寄存器文件访问电路将程序使用的虚拟寄存器编号映射到硬件寄存器文件中。从过程返回时，通过将寄存器堆栈指针调整到调用过程时存储的值来释放寄存器。

8. 发明授权

US5721498A Block segmentation of configuration lines for fault tolerant programmable logic device 失效
公开(公告)号：US5721498A
公开(公告)日：1998-02-24
申请号：US570035
申请日：1995-12-11
申请人： William R. Mason , Frederic C. Amerson
发明人： William R. Mason , Frederic C. Amerson
IPC分类号： H01L21/82 , H01L21/8244 , H01L27/11 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17704 , H03K19/17764
摘要： A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.

9. 发明授权

US5945841A Block segmentation of configuration lines for fault tolerant programmable logic device 失效
标题翻译：用于容错可编程逻辑器件的配置线的块分割
公开(公告)号：US5945841A
公开(公告)日：1999-08-31
申请号：US941428
申请日：1997-09-30
申请人： William R. Mason , Frederic C. Amerson
发明人： William R. Mason , Frederic C. Amerson
IPC分类号： H01L21/82 , H01L21/8244 , H01L27/11 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17704 , H03K19/17764
摘要： A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.
摘要翻译：一种包括以块组织的多个可编程瓦片的可编程逻辑器件（PLD）。每个块包括多个可编程瓦片的唯一子集。数据总线延伸到每个块。在每个块内提供一个独立的地址电路。块选择线耦合到每个块，使得当块选择线被断言时，所选块的地址电路能够将数据从数据总线传送到多个可编程块，并且当块使能线被解除时，数据总线与地址电路和数据总线实质上电隔离。

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