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1. 发明授权

US06801437B2 Electronic organic substrate 失效
公开(公告)号：US06801437B2
公开(公告)日：2004-10-05
申请号：US10347759
申请日：2003-01-21
申请人： Maurice O. Othieno , Manickam Thavarajah , Severino A. Legaspi, Jr. , Pradip D. Patel
发明人： Maurice O. Othieno , Manickam Thavarajah , Severino A. Legaspi, Jr. , Pradip D. Patel
IPC分类号： H05K118
CPC分类号： H05K3/28 , H05K3/0023 , H05K3/064 , H05K3/243 , H05K2201/0195 , H05K2201/09881 , H05K2203/0759
摘要： A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers. Both the second layer and the third layer of photo imageable ink are retained on the electronic substrate.

2. 发明授权

US06867480B2 Electromagnetic interference package protection 有权
标题翻译：电磁干扰封装保护
公开(公告)号：US06867480B2
公开(公告)日：2005-03-15
申请号：US10458130
申请日：2003-06-10
申请人： Severino A. Legaspi, Jr. , Manickam Thavarajah , Maurice O. Othieno , Pradip D. Patel
发明人： Severino A. Legaspi, Jr. , Manickam Thavarajah , Maurice O. Othieno , Pradip D. Patel
IPC分类号： H01L23/29 , H01L23/31 , H01L23/552
CPC分类号： H01L23/552 , H01L23/295 , H01L23/3135 , H01L24/48 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.
摘要翻译：一种屏蔽集成电路免受电磁干扰的方法。集成电路至少部分地封装在耐电磁干扰模塑料中，然后将集成电路完全封装在第二模塑料中。以这种方式，抗电磁干扰模塑料保护集成电路免受电磁干扰，而可以选择第二模塑料用于模塑料中传统上期望的性能，例如热，电绝缘和结构性能。因此，根据本发明的集成电路可以更靠近产生电磁干扰的结构，例如电源，而不会由于由结构引起的电磁干扰而经受不可接受的性能劣化。

3. 发明授权

US06603201B1 Electronic substrate 有权
标题翻译：电子基板
公开(公告)号：US06603201B1
公开(公告)日：2003-08-05
申请号：US10278373
申请日：2002-10-23
申请人： Manickam Thavarajah , Maurice O. Othieno , Severino A. Legaspi, Jr. , Pradip D. Patel
发明人： Manickam Thavarajah , Maurice O. Othieno , Severino A. Legaspi, Jr. , Pradip D. Patel
IPC分类号： H01L2312
CPC分类号： H05K1/0366 , H01L2224/16237 , H05K1/0271 , H05K3/4626 , H05K3/4688 , H05K2201/029 , H05K2201/09145
摘要： A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.
摘要翻译：具有侧面的封装衬底，其由多个非导电层形成，层叠在一起。多个非导电层中的每一个由在树脂基体中结合在一起的第一层和第二层形成。第一层由具有第一翘曲的编织纤维形成。第一层板的第一翘曲从封装基板的侧面以第一角度的正方向设置，其中第一角度既不是零度也不是九十度。第二层也由具有第二翘曲的编织纤维形成。第二层板的第二翘曲被设置在与封装衬底的侧面成第一角度的负取向。导电层分散在多个非导电层中的不同导电层之间，电连接分散在不同的导电层之间。

4. 发明授权

US06555914B1 Integrated circuit package via 有权
标题翻译：集成电路封装通过
公开(公告)号：US06555914B1
公开(公告)日：2003-04-29
申请号：US09975871
申请日：2001-10-12
申请人： Aritharan Thurairajaratnam , Pradip D. Patel , Manickam Thavarajah , Hong T. Lim
发明人： Aritharan Thurairajaratnam , Pradip D. Patel , Manickam Thavarajah , Hong T. Lim
IPC分类号： H01L2352
CPC分类号： H05K1/116 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/429 , H05K2201/09545 , H05K2201/09718 , H01L2924/00
摘要： A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole. The parasitic capacitance of the via is reduced by not having via lands on the secondary layers.
摘要翻译：一种在电路中形成通孔的方法，使得寄生电容减小。识别电路的表面层，对通孔的连续性是期望的，并且还识别电路的次级层。通常的焊盘只形成在表面层上，而不是在次级层上形成。通孔焊盘形成在表面层的第一部分中，其中通孔将通过表面层。在第二层的第二部分中形成非导电切口，其中通孔将通过次级层。电路的表面层和次级层叠在一起。表层的第一部分与第二层的第二部分对准。通过形成在表面层中的通孔接合区以及通过形成在次级层中的切口形成通孔。通孔形成在通孔中。通过在二级层上没有通孔焊盘来减小通孔的寄生电容。

5. 发明申请

US20090096092A1 Bump I/O Contact for Semiconductor Device 有权
标题翻译：半导体器件的凸起I / O触点
公开(公告)号：US20090096092A1
公开(公告)日：2009-04-16
申请号：US11871096
申请日：2007-10-11
申请人： Pradip D. Patel
发明人： Pradip D. Patel
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/05568 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13007 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13181 , H01L2224/16058 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/00014 , H01L2924/01083 , H01L2924/01007 , H01L2224/13099
摘要： A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.
摘要翻译：凸点接触电连接基板上的导体和安装到基板的半导体器件上的接触焊盘。导电柱的第一端使柱与电接触垫的电接触和机械连接，柱从半导体器件向外突出。在预定温度下可回流的焊接表面与导体实现电接触和机械附接定位成与柱的第二端轴向对准。扩散阻挡层电气地和机械地将焊料凸块连接到柱的第二端，并抵抗从柱子进入到铜的焊锡冠的第一端的电迁移。一个扩散阻挡层是位于柱和焊料冠之间的镍，钯，钛 - 钨，镍 - 钒或氮化钽的2-20微米厚对照层的形式。

6. 发明授权

US08269345B2 Bump I/O contact for semiconductor device 有权
标题翻译：半导体器件的凸起I / O触点
公开(公告)号：US08269345B2
公开(公告)日：2012-09-18
申请号：US11871096
申请日：2007-10-11
申请人： Pradip D. Patel
发明人： Pradip D. Patel
IPC分类号： H01L23/52 , H01L21/00 , H01L23/48 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/05568 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13007 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13181 , H01L2224/16058 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/00014 , H01L2924/01083 , H01L2924/01007 , H01L2224/13099
摘要： A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.
摘要翻译：凸点接触电连接基板上的导体和安装到基板的半导体器件上的接触焊盘。导电柱的第一端使柱与电接触垫的电接触和机械连接，柱从半导体器件向外突出。在预定温度下可回流的焊接表面与导体实现电接触和机械附接定位成与柱的第二端轴向对准。扩散阻挡层电气地和机械地将焊料凸块连接到柱的第二端，并抵抗从柱子进入到铜的焊锡冠的第一端的电迁移。一个扩散阻挡层是位于柱和焊料冠之间的镍，钯，钛 - 钨，镍 - 钒或氮化钽的2-20微米厚对照层的形式。

7. 发明授权

US5541524A Burn-in technologies for unpackaged integrated circuits 失效
公开(公告)号：US5541524A
公开(公告)日：1996-07-30
申请号：US125941
申请日：1993-09-23
申请人： David B. Tuckerman , Pradip D. Patel
发明人： David B. Tuckerman , Pradip D. Patel
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2863 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48472 , H01L2224/73265 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/30107
摘要： A device and method for burn-in of bare chips prior to assembly into a multichip module. Each die to be tested is positioned with its I/O pads positioned to face an interconnection burn-in test substrate which may be a silicon circuit board. Each die is temporarily electrically connected to the substrate by a deformable solder bump.

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