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1. 发明申请

US20080308783A1 Memory devices and methods of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080308783A1
公开(公告)日：2008-12-18
申请号：US12213062
申请日：2008-06-13
申请人： Seung-eon Ahn , Myoung-jae Lee , Suk-pil Kim , Young-soo Park
发明人： Seung-eon Ahn , Myoung-jae Lee , Suk-pil Kim , Young-soo Park
IPC分类号： H01L47/00 , H01L29/76 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/72 , H01L27/24
摘要： Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other.
摘要翻译：提供了存储器件及其制造方法。在存储器件中，在第一和第二电极之间形成存储器开关结构。存储器开关结构包括存储器电阻器和开关结构。开关结构控制提供给存储电阻的电流。存储电阻的存储区域和开关结构的开关区域彼此不同。

2. 发明授权

US08274067B2 Memory devices and methods of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08274067B2
公开(公告)日：2012-09-25
申请号：US12213062
申请日：2008-06-13
申请人： Seung-eon Ahn , Myoung-jae Lee , Suk-pil Kim , Young-soo Park
发明人： Seung-eon Ahn , Myoung-jae Lee , Suk-pil Kim , Young-soo Park
IPC分类号： H01L29/06
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/72 , H01L27/24
摘要： Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other.
摘要翻译：提供了存储器件及其制造方法。在存储器件中，在第一和第二电极之间形成存储器开关结构。存储器开关结构包括存储器电阻器和开关结构。开关结构控制提供给存储电阻的电流。存储电阻的存储区域和开关结构的开关区域彼此不同。

3. 发明授权

US07910967B2 Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same 失效
标题翻译：具有三维结构的铁电电容器，具有相同的非易失性存储器件及其制造方法
公开(公告)号：US07910967B2
公开(公告)日：2011-03-22
申请号：US11515024
申请日：2006-09-05
申请人： Sang-min Shin , Young-soo Park , June-mo Koo , Byoung-jae Bae , I-hun Song , Suk-pil Kim
发明人： Sang-min Shin , Young-soo Park , June-mo Koo , Byoung-jae Bae , I-hun Song , Suk-pil Kim
IPC分类号： H01L21/00 , H01L31/112 , H01L23/48
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.
摘要翻译：提供具有三维结构的铁电电容器，具有其的非易失性存储器件及其制造方法。铁电电容器可以包括沟槽型下电极，形成在下电极周围的至少一层，形成在下电极和至少一层上的铁电层（PZT层）和形成在铁电层上的上电极。所述至少一个层可以是至少一个绝缘夹层，并且所述至少一个层也可以是至少一个扩散阻挡层。所述至少一层可以由除了SiO2之外的绝缘材料形成，或者可以具有不包括Pb的钙钛矿晶体结构。

4. 发明申请

US20060027847A1 Ferroelectric memory and ferroelectric capacitor with Ir-alloy electrode or Ru-alloy electrode and method of manufacturing same 有权
公开(公告)号：US20060027847A1
公开(公告)日：2006-02-09
申请号：US11193415
申请日：2005-08-01
申请人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
发明人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/65
摘要： A ferroelectric capacitor comprises a first electrode comprising an alloy containing a first element and a second element of the periodic table of the elements, the first element being selected from the group consisting of Ir and Ru. A ferroelectric layer is disposed on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material containing the second element. A second electrode is disposed on the ferroelectric layer. The ferroelectric capacitor can be provided as part of a memory cell of a ferroelectric memory.

5. 发明授权

US07682758B2 Reflection mask for EUV photolithography and method of fabricating the reflection mask 有权
标题翻译：用于EUV光刻的反射掩模和制造反射掩模的方法
公开(公告)号：US07682758B2
公开(公告)日：2010-03-23
申请号：US11441835
申请日：2006-05-26
申请人： Suk-pil Kim , I-hun Song , Young-soo Park , Seung-hyuk Chang , Hoon Kim
发明人： Suk-pil Kim , I-hun Song , Young-soo Park , Seung-hyuk Chang , Hoon Kim
IPC分类号： G03F1/00
CPC分类号： G21K1/062 , B82Y10/00 , B82Y40/00 , G03F1/24
摘要： A reflection mask for extreme ultraviolet (EUV) photolithography and a method of fabricating the same, in which the reflection mask includes a substrate, a lower reflection layer formed in a multi-layer structure on the substrate and including a material reflecting EUV light, an upper reflection layer formed in a multi-layer structure on the lower reflection layer and reflecting EUV light, and a phase reversing layer formed between the lower reflection layer and the upper reflection layer in a certain pattern and causing destructive interference between reflection light from the upper reflection layer and reflection light from the lower reflection layer. An incidence of a shadow effect can be reduced and unnecessary EUV light can be eliminated, so that a pattern on the reflection mask can be projected precisely on a silicon wafer. Since the phase reversing layer includes the same material as the reflection layer and an absorption layer, mask fabrication processes can be handled easily.
摘要翻译：一种用于极紫外（EUV）光刻的反射掩模及其制造方法，其中反射掩模包括基板，在基板上形成为多层结构的下反射层，并且包括反射EUV光的材料，在下反射层上形成多层结构并反射EUV光的上反射层和以一定图案形成在下反射层和上反射层之间的相位反转层，并且产生来自上层的反射光之间的相消干涉反射层和来自下反射层的反射光。可以减少阴影效应的入射，并且可以消除不必要的EUV光，使得反射掩模上的图案可以精确地投影在硅晶片上。由于相位反转层包括与反射层和吸收层相同的材料，因此可以容易地处理掩模制造工艺。

6. 发明申请

US20060090702A1 Duplex chemical vapor deposition system and pulsed processing method using the same 审中-公开
标题翻译：双相化学气相沉积系统和使用其的脉冲处理方法
公开(公告)号：US20060090702A1
公开(公告)日：2006-05-04
申请号：US11185689
申请日：2005-07-21
申请人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
发明人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
IPC分类号： C23C16/00
CPC分类号： C23C16/409 , C23C16/44
摘要： Embodiments are provided of a duplex chemical vapor deposition (CVD) system and pulsed processing method using the same. The duplex CVD system may include first and second process chambers, one or more reactive sources, and reactive source suppliers that correspond to the reactive sources, respectively. The reactive source suppliers may include a first conduit portion connected to the respective reactive sources, a second conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the first process chamber, and a third conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the second process chamber.
摘要翻译：提供了双相化学气相沉积（CVD）系统和使用其的脉冲处理方法的实施例。双相CVD系统可以分别包括对应于无源电源的第一和第二处理室，一个或多个无源电源和无源电源供应器。反应源供应商可以包括连接到各个反应源的第一管道部分，具有连接到第一管道部分的一个端子和连接到第一处理室的另一个端子的第二管道部分，以及一个端子连接的第三管道部分连接到第二处理室的第一管道部分和另一个端子。

7. 发明申请

US20060001070A1 Capacitor of a memory device and fabrication method thereof 失效
标题翻译：存储器件的电容器及其制造方法
公开(公告)号：US20060001070A1
公开(公告)日：2006-01-05
申请号：US11120184
申请日：2005-05-03
申请人： Young-soo Park , Jung-hyun Lee , Choong-rae Cho , June-mo Koo , Suk-pil Kim , Sang-min Shin
发明人： Young-soo Park , Jung-hyun Lee , Choong-rae Cho , June-mo Koo , Suk-pil Kim , Sang-min Shin
IPC分类号： H01L21/00 , H01L27/108
CPC分类号： H01L28/91 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.
摘要翻译：存储器件的电容器及其制造方法包括电耦合到晶体管结构的掺杂区域的下电极，下电极具有金属电极和金属氧化物电极，铁电层覆盖并横向延伸沿着下电极和形成在铁电层上的上电极。

8. 发明申请

US20070031741A1 EUVL reflection device, method of fabricating the same, and mask, projection optics system and EUVL apparatus using the EUVL reflection device 审中-公开
标题翻译： EUVL反射装置及其制造方法，掩模，投影光学系统和使用EUVL反射装置的EUVL装置
公开(公告)号：US20070031741A1
公开(公告)日：2007-02-08
申请号：US11498020
申请日：2006-08-03
申请人： Hoon Kim , Suk-pil Kim , I-hun Song , Young-soo Park , Seung-hyuk Chang
发明人： Hoon Kim , Suk-pil Kim , I-hun Song , Young-soo Park , Seung-hyuk Chang
IPC分类号： G02B5/20 , F21V9/06 , F21V9/04 , G21K5/00 , G03F1/00 , G02B5/08
CPC分类号： G03F1/24 , B82Y10/00 , B82Y40/00 , G03F7/70316 , G03F7/70958 , G21K1/062
摘要： A reflection device that may include a substrate and a multi-reflection layer formed on the substrate. The multi-reflection layer may be formed of a material capable of reflecting EUV rays. The multi-reflection layer may be formed by stacking a plurality of layer groups, each including a first material layer, a surface-treated layer obtained by surface-treating the first material layer, and a second material layer formed on the surface-treated layer. A method of fabricating the reflection device that may include preparing a substrate and forming a multi-reflection layer on the substrate from a material capable of reflecting EUV rays. The forming of the multi-reflection layer may be performed by repeatedly forming a layer group. The forming of the layer group may include forming a first material layer, surface-treating the first material layer, and forming a second material layer on the surface-treated first material layer.
摘要翻译：可以包括形成在基板上的基板和多反射层的反射装置。多反射层可以由能够反射EUV射线的材料形成。多反射层可以通过层叠多个层组而形成，每个层组包括第一材料层，通过表面处理第一材料层获得的表面处理层和形成在表面处理层上的第二材料层。一种制造反射装置的方法，其可以包括准备基板并且在能够反射EUV射线的材料的基板上形成多反射层。多反射层的形成可以通过重复形成层组来进行。层组的形成可以包括形成第一材料层，对第一材料层进行表面处理，以及在表面处理的第一材料层上形成第二材料层。

9. 发明申请

US20070012974A1 Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof 审中-公开
标题翻译：用于制造材料层的方法，使用该方法制造铁电电容器的方法，通过相同方法制造的铁电电容器，具有铁电电容器的半导体存储器件及其制造方法
公开(公告)号：US20070012974A1
公开(公告)日：2007-01-18
申请号：US11484582
申请日：2006-07-12
申请人： June-mo Koo , Bum-seok Seo , Young-soo Park , Jung-hyun Lee , Sang-min Shin , Suk-pil Kim
发明人： June-mo Koo , Bum-seok Seo , Young-soo Park , Jung-hyun Lee , Sang-min Shin , Suk-pil Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/02197 , H01L21/0228 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.
摘要翻译：提供一种能够提高强电介质层上的贵金属层的沉积速度的材料层的制造方法，使用该材料的铁电电容器的制造方法，通过相同的方法制造的铁电电容器以及半导体存储器件具有铁电电容器及其制造方法。根据材料层的制造方法，形成铁电体层。可以将铁电层暴露于种子等离子体，并且可以在暴露于种子等离子体的铁电层的区域上形成包括种子等离子体的源材料的材料层。

10. 发明申请

US20060022236A1 Ferroelectric capacitor and ferroelectric memory with Ir-Ru alloy electrode and method of manufacturing the same 有权
公开(公告)号：US20060022236A1
公开(公告)日：2006-02-02
申请号：US10978795
申请日：2004-11-02
申请人： Sang-min Shin , Suk-pil Kim , Young-soo Park , Jung-hyun Lee , June-mo Koo
发明人： Sang-min Shin , Suk-pil Kim , Young-soo Park , Jung-hyun Lee , June-mo Koo
IPC分类号： H01L29/76
CPC分类号： H01L27/11502 , H01L28/55 , H01L28/65 , Y10T29/417
摘要： A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

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