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1. 发明申请

US20050139862A1 Self-aligned heterojunction bipolar transistor and manufacturing method thereof 审中-公开
标题翻译：自对准异质结双极晶体管及其制造方法
公开(公告)号：US20050139862A1
公开(公告)日：2005-06-30
申请号：US10677665
申请日：2003-10-01
申请人： Chan Park , Seung-Yun Lee , Shanghoon Kim , Jin-Yeong Kang
发明人： Chan Park , Seung-Yun Lee , Shanghoon Kim , Jin-Yeong Kang
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737 , H01L29/739 , H01L31/0328 , H01L31/072
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： Provided are a self-aligned heterojunction bipolar transistor that can prevent electrical short-circuit caused by the agglomeration during the formation of a silicide electrode, minimize resistance by forming thick base electrodes, minimize the parasitic resistance of the base and parasitic capacitance between the base and the collector, and thus improve the process stability and economical efficiency by ruling out a wet-etching process and performing a selective thin film growing process once, and a manufacturing method thereof. The heterojunction bipolar transistor of this research includes: a collector and a collector electrode formed within a silicon substrate; base electrodes formed on the collector and including a protrusion having a first opening and a body having a second opening for exposing the surface of the collector; a base epitaxial layer grown selectively on the collector exposed thorough the first opening; sidewall spacers formed on the sidewalls of the second opening; an emitter electrode formed on the base epitaxial layer in the shape of an overhang that covers the sidewall spacers; and an insulation layer inserted between the overhang of the emitter electrode and the base electrodes and connected to the sidewall spacers.
摘要翻译：提供了一种自对准异质结双极晶体管，其可以防止在形成硅化物电极期间由聚集引起的电短路，通过形成厚的基极电极使电阻最小化，使基极的寄生电阻最小化，并且基极和并且因此通过排除湿式蚀刻工艺和执行选择性薄膜生长工艺一次来提高工艺稳定性和经济性及其制造方法。该研究的异质结双极晶体管包括：在硅衬底内形成的集电极和集电极; 基底电极形成在集电体上并且包括具有第一开口的突起和具有用于暴露集电体的表面的第二开口的主体; 在通过第一开口暴露的收集器上选择性地生长的基极外延层; 形成在第二开口的侧壁上的侧壁间隔物; 形成在所述基底外延层上的覆盖所述侧壁间隔物的突出形状的发射电极; 以及绝缘层，其插入在发射电极的伸出部和基极之间并与侧壁间隔件连接。

2. 发明授权

US06469609B2 Method of fabricating silver inductor 有权
标题翻译：制造银电感的方法
公开(公告)号：US06469609B2
公开(公告)日：2002-10-22
申请号：US09733839
申请日：2000-12-07
申请人： Seung-Yun Lee , Jin-Yeong Kang
发明人： Seung-Yun Lee , Jin-Yeong Kang
IPC分类号： H01F500
CPC分类号： H01F41/041 , H01F5/003 , Y10T29/4902 , Y10T29/49071
摘要： The present invention relates to a method of fabricating an inductor capable of improving a quality factor and decreasing a series resistance by using as a material of the inductor silver smaller in a specific resistance than aluminum used conventionally. The method of fabricating an inductor according to the present invention includes the following steps. A first step is of forming a first metal layer on a first insulating layer, patterning said first metal layer, and forming a second insulating layer on the resultant structure. A second step is of patterning said second insulating layer to form a via hole and forming a plug in said via hole. A third step is of forming a third insulating layer on the resultant structure and patterning said third insulating layer to form a spiral groove. A fourth step is of forming a second metal layer in said spiral groove to form an inductor. And a fifth step is of forming a fourth insulating layer for protecting said inductor from a mechanical force or materials causing a chemical reaction.
摘要翻译：本发明涉及一种制造电感器的方法，该电感器通过使用电感器银的材料，其电阻比常规使用的铝的电阻率小，可以提高品质因数并降低串联电阻。根据本发明的制造电感器的方法包括以下步骤。第一步骤是在第一绝缘层上形成第一金属层，图案化所述第一金属层，并在所得结构上形成第二绝缘层。第二步是图案化所述第二绝缘层以形成通孔并在所述通孔中形成插头。第三步骤是在所得结构上形成第三绝缘层，并且图案化所述第三绝缘层以形成螺旋槽。第四步骤是在所述螺旋槽中形成第二金属层以形成电感器。并且第五步是形成用于保护所述电感器免受机械力或导致化学反应的材料的第四绝缘层。

3. 发明授权

US08872146B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US08872146B2
公开(公告)日：2014-10-28
申请号：US12821414
申请日：2010-06-23
申请人： Seung-Yun Lee , Young Sam Park , Sung Min Yoon , Kyu-Jeong Choi , Nam-Yeal Lee , Byoung-Gon Yu
发明人： Seung-Yun Lee , Young Sam Park , Sung Min Yoon , Kyu-Jeong Choi , Nam-Yeal Lee , Byoung-Gon Yu
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Provided are a Phase-change Random Access Memory (PRAM) device and a method of manufacturing the same. In particular, a PRAM device including a heating layer, wherein the heating layer comprises first and second heating layers having different physical properties from each other and a method of manufacturing the same are provided. Since the PRAM device according to the present invention includes a heating layer having optimal heating characteristics, a PRAM device having high reliability and excellent operating characteristics can be manufactured.
摘要翻译：提供了一种相变随机存取存储器（PRAM）装置及其制造方法。特别地，包括加热层的PRAM装置及其制造方法，其中加热层包括彼此具有不同物理性质的第一和第二加热层。由于根据本发明的PRAM器件包括具有最佳加热特性的加热层，所以可以制造具有高可靠性和优异的工作特性的PRAM器件。

4. 发明申请

US20100010954A1 DEVICE AND METHOD OF PROCESSING RULES BASED ON WEB SERVICES 有权
标题翻译：基于WEB服务处理规则的设备和方法
公开(公告)号：US20100010954A1
公开(公告)日：2010-01-14
申请号：US12517671
申请日：2007-08-22
申请人： Kangchan Lee , Won-Suk Lee , Jong-Hong Jeon , Seung-Yun Lee
发明人： Kangchan Lee , Won-Suk Lee , Jong-Hong Jeon , Seung-Yun Lee
IPC分类号： G06N5/02
CPC分类号： H04L67/02 , G06F17/3089 , H04L67/32
摘要： Provided is a device for storing a rule describing an event, a condition to be satisfied by the event, and an action to be executed when the condition is satisfied and executing the action of the rule in an expended structure for using web services so as to effectively process the web services in various devices as well as a computer. In addition, a global rule manager for inspecting the validity of the rule when the rule is stored and executed is provided. Accordingly, the web services can be effectively used in a ubiquitous environment.
摘要翻译：提供了一种用于存储描述事件的规则，事件要满足的条件的装置，以及当条件满足时要执行的动作，并且在使用web服务的消耗结构中执行规则的动作，以便有效地处理各种设备以及计算机中的Web服务。另外，提供了一个全局规则管理器，用于在存储和执行规则时检查规则的有效性。因此，Web服务可以在无所不在的环境中有效地使用。

5. 发明授权

US07920413B2 Apparatus and method for writing data to phase-change memory by using power calculation and data inversion 有权
标题翻译：通过使用功率计算和数据反演将数据写入相变存储器的装置和方法
公开(公告)号：US07920413B2
公开(公告)日：2011-04-05
申请号：US12040137
申请日：2008-02-29
申请人： Byoung-Gon Yu , Byung-Do Yang , Seung-Yun Lee , Sung-Min Yoon , Young Sam Park , Nam Yeal Lee
发明人： Byoung-Gon Yu , Byung-Do Yang , Seung-Yun Lee , Sung-Min Yoon , Young Sam Park , Nam Yeal Lee
IPC分类号： G11C11/00
CPC分类号： G11C7/1006 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2211/5647
摘要： Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time. According to the present invention, since the PRAM consumes different amounts of power when writing data with a value of 0 and data with a value of 1, the power consumed when input original data is stored and the power consumed when the input original data is inverted and stored are compared to each other, the data with a smaller power consumption is stored when the data is written to the PRAM as a word unit, and thus the power consumption of the PRAM can be reduced.
摘要翻译：提供了一种通过使用写入功率计算和数据反转功能将数据写入相变随机存取存储器（PRAM）的装置和方法，更具体地，涉及一种用于写入数据的装置和方法，该装置和方法可通过计算功率来最小化功耗在输入原始数据或反相数据被写入PRAM并存储消耗较少功率的数据时消耗。由于需要大电流长时间流动，所以PRAM消耗大量的功率以便将数据存储在存储单元中。根据本发明，由于在写入值为0的数据和值为1的数据时，PRAM消耗不同的功率量，所以当输入原始数据被存储时消耗的功率和当输入的原始数据被反相时消耗的功率并将其进行存储，将数据作为字单元写入PRAM时，存储具有较小功耗的数据，从而能够降低PRAM的功耗。

6. 发明授权

US07911227B2 Programmable logic block of FPGA using phase-change memory device 有权
标题翻译：使用相变存储器件的FPGA的可编程逻辑块
公开(公告)号：US07911227B2
公开(公告)日：2011-03-22
申请号：US12633731
申请日：2009-12-08
申请人： Byoung Gon Yu , Yong-Joo Kim , Sung Min Yoon , Seung-Yun Lee , Young Sam Park , Soonwon Jung
发明人： Byoung Gon Yu , Yong-Joo Kim , Sung Min Yoon , Seung-Yun Lee , Young Sam Park , Soonwon Jung
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17784 , H03K19/17728 , H03K19/17792
摘要： Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
摘要翻译：提供了现场可编程门阵列（FPGA）的可编程逻辑块。可编程逻辑块包括连接到电源的上拉访问晶体管，连接到上拉存取晶体管的上变相存储器件，连接到上变相存储晶体管的下变相存储器件存储器件，上变相存储器件和下变相存储器件之间的输出端子以及连接到下变相存储器件和地的下拉存取晶体管。上变相存储器件和下变相存储器件的电阻值被单独编程。

7. 发明授权

US06752874B2 Apparatus for perpendicular-type ultra vacuum chemical vapor deposition 失效
标题翻译：垂直型超真空化学气相沉积设备
公开(公告)号：US06752874B2
公开(公告)日：2004-06-22
申请号：US09789890
申请日：2001-02-20
申请人： Kyu-Hwan Shim , Hong-Seung Kim , Seung-Yun Lee , Jin-Yeoung Kang
发明人： Kyu-Hwan Shim , Hong-Seung Kim , Seung-Yun Lee , Jin-Yeoung Kang
IPC分类号： C23C16000
CPC分类号： H01L21/67757 , C23C16/4401 , C23C16/46 , C23C16/54 , C30B25/02
摘要： The apparatus for a perpendicular type ultra vacuum chemical vapor deposition, which is for growing an epitaxy crystal as a semiconductor thin film based on a high quality, includes a growth chamber having a quartz tube of a heterostructure for maintaining a uniformity in a growth of an epitaxial layer under a high vacuum and minimizing a thermal transfer from a wafer; a wafer transferring chamber having a perpendicular transfer device for vertically transferring the wafer on which the epitaxial layer grows; a buffer chamber for preventing a stress to a transfer gear caused by a pressure difference with the wafer transferring chamber in vertically transferring the wafer; and a loadlock chamber for reducing a pollution from the outside in the growth of the epitaxial layer, horizontally transferring the wafer completed in the growth of the epitaxial layer, and discharging it to the outside.
摘要翻译：用于生长基于高质量的半导体薄膜的外延晶体的用于垂直型超真空化学气相沉积的装置包括具有异质结构的石英管的生长室，用于保持生长中的均匀性外延层，并使来自晶片的热传递最小化; 晶片传送室具有用于垂直传送其上外延层生长的晶片的垂直转移装置; 缓冲室，用于在垂直传送晶片时防止与晶片传送室的压力差导致的传递齿轮的应力; 以及负载锁定室，用于在外延层的生长中减少来自外部的污染，水平地转移在外延层的生长中完成的晶片，并将其放电到外部。

8. 发明授权

US6057228A Method of forming interconnection for semiconductor device 有权
标题翻译：形成半导体器件互连的方法
公开(公告)号：US6057228A
公开(公告)日：2000-05-02
申请号：US140834
申请日：1998-08-26
申请人： Seung-Yun Lee , Yong-Sup Hwang , Chong-Ook Park , Dong-Won Kim , Sa-Kyun Rha , Jun-Ki Kim
发明人： Seung-Yun Lee , Yong-Sup Hwang , Chong-Ook Park , Dong-Won Kim , Sa-Kyun Rha , Jun-Ki Kim
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76838 , H01L23/53228 , H01L2924/0002
摘要： The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.
摘要翻译：本发明涉及使用铜形成半导体器件互连的方法。本发明的方法包括以下步骤：在包含有源元件的半导体衬底上形成具有凹槽的绝缘层; 在包括所述槽的所述绝缘层上形成和沉积铜薄膜; 并且回流铜薄膜时，可以使沉积在具有高阶表面的半导体衬底上的铜薄膜回流少于30分钟。低于450℃，与现有技术相比显示出改善的退火条件。此外，通过根据低温处理减少热能消耗，在形成半导体器件的互连时，抑制铜通过硅衬底，电极等快速扩散，从而提高半导体器件的生产率。

9. 发明申请

US20100325696A1 SYSTEM FOR AUTHENTICATION OF CONFIDENCE LINK AND METHOD FOR AUTHENTICATION AND INDICATING AUTHENTICATION THEREOF 审中-公开
标题翻译：认证链接认证系统及其认证及其认证方法
公开(公告)号：US20100325696A1
公开(公告)日：2010-12-23
申请号：US12518058
申请日：2006-12-06
申请人： Jong-Hong Jeon , Won-Suk Lee , Kang-chan Lee , Seung-Yun Lee , Min-Kyo In , Tae-Wan You , In-Dong Jang
发明人： Jong-Hong Jeon , Won-Suk Lee , Kang-chan Lee , Seung-Yun Lee , Min-Kyo In , Tae-Wan You , In-Dong Jang
IPC分类号： G06F21/00 , G06F15/16
CPC分类号： H04L63/1483 , G06F21/31 , G06F21/51 , G06F2221/2115 , G06F2221/2119
摘要： In a certified link authentication system, a terminal parses a web page and extracts markup information for a certified link. In addition, the terminal transmits the extracted markup information to a certified link authentication server. The certified link authentication server authenticates the certified link from the markup information of the certified link transmitted from the terminal, and transmits an authentication result to the terminal. The terminal marks the authenticated certified link with a certified mark, renders the web page, and displays it to the user.
摘要翻译：在认证链路认证系统中，终端解析网页并提取认证链路的标记信息。此外，终端将提取的标记信息发送到经认证的链路认证服务器。经认证的链路认证服务器根据从终端发送的认证链路的标识信息对认证链路进行认证，并将认证结果发送给终端。终端通过认证标记标识经认证的认证链接，呈现网页，并将其显示给用户。

10. 发明申请

US20070283242A1 Xml Processor and Xml Processing Method in System Having the Xml Processor 审中-公开
标题翻译： Xml处理器和具有Xml处理器的系统中的Xml处理方法
公开(公告)号：US20070283242A1
公开(公告)日：2007-12-06
申请号：US10584733
申请日：2004-10-29
申请人： Kang-Chan Lee , Jong-Hong Jeon , Won-Suk Lee , Seung-Yun Lee , Ki-Shik Park
发明人： Kang-Chan Lee , Jong-Hong Jeon , Won-Suk Lee , Seung-Yun Lee , Ki-Shik Park
IPC分类号： G06F15/00
CPC分类号： G06F17/2247 , G06F17/272
摘要： A significant drawback of the conventional XML parsers is that such parsers require relatively large software components, which causes load of a system that processes the XML documents to increase. Provided is an XML processor in which a part of XML processing is performed in a hardware manner based on independent hardware, thereby reducing computational load of a system and improving an XML processing speed, and an XML processing method performed in a system having the XML processor. The XML processor includes: a first memory storing software for performing an XML processing, variables, and values required to execute software; a hardware processing module performing a part of the XML processing in a hardware manner; a second memory employed by the hardware processing module; and a CPU controlling the XML processing by the software stored in the first memory. An XML processor in which a part of XML processing is performed in a hardware manner based on independent hardware, thereby improving an XML processing speed and reducing load of system compared to the conventional software processing.
摘要翻译：常规XML解析器的一个显着缺点是，这种解析器需要相对较大的软件组件，这导致处理XML文档的系统的加载增加。提供了一种XML处理器，其中基于独立硬件以硬件方式执行部分XML处理，从而减少系统的计算负担并提高XML处理速度，以及在具有XML处理器的系统中执行的XML处理方法。 XML处理器包括：存储用于执行执行软件所需的XML处理，变量和值的软件的第一存储器; 硬件处理模块以硬件方式执行XML处理的一部分; 由硬件处理模块采用的第二存储器; 以及CPU，其通过存储在第一存储器中的软件来控制XML处理。一种XML处理器，其中基于独立硬件以硬件方式执行部分XML处理，从而与常规软件处理相比提高了XML处理速度并降低了系统负载。

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