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1. 发明授权

US08233339B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08233339B2
公开(公告)日：2012-07-31
申请号：US12875803
申请日：2010-09-03
申请人： Hyun-Su Yoon , Jong-Chern Lee , Seung-Joon Ahn
发明人： Hyun-Su Yoon , Jong-Chern Lee , Seung-Joon Ahn
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
摘要翻译：半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令对应于第二延迟量，并且输出控制哪个操作定时的命令。

2. 发明申请

US20120008433A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120008433A1
公开(公告)日：2012-01-12
申请号：US12875803
申请日：2010-09-03
申请人： Hyun-Su YOON , Jong-Chern Lee , Seung-Joon Ahn
发明人： Hyun-Su YOON , Jong-Chern Lee , Seung-Joon Ahn
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
摘要翻译：半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令对应于第二延迟量，并且输出控制哪个操作定时的命令。

3. 发明授权

US08482331B2 Open loop type delay locked loop and method for operating the same 失效
标题翻译：开环型延时锁定环及其操作方法
公开(公告)号：US08482331B2
公开(公告)日：2013-07-09
申请号：US12832549
申请日：2010-07-08
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K2005/00104
摘要： An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
摘要翻译：开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟响应代码值。

4. 发明授权

US08451037B2 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08451037B2
公开(公告)日：2013-05-28
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

5. 发明申请

US20120154002A1 DELAY LOCKED LOOP 失效
标题翻译：延迟锁定环
公开(公告)号：US20120154002A1
公开(公告)日：2012-06-21
申请号：US13400967
申请日：2012-02-21
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03L7/08
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

6. 发明授权

US08143925B2 Delay locked loop 失效
标题翻译：延迟锁定环路
公开(公告)号：US08143925B2
公开(公告)日：2012-03-27
申请号：US12753442
申请日：2010-04-02
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

7. 发明授权

US08446197B2 Delay locked loop and method for driving the same 有权
标题翻译：延迟锁定环和驱动方法
公开(公告)号：US08446197B2
公开(公告)日：2013-05-21
申请号：US12755949
申请日：2010-04-07
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/07
摘要： A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.
摘要翻译：延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。编码单元被配置为对延迟脉冲进行编码并输出代码值。延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

8. 发明授权

US08242822B2 Delay locked loop 失效
公开(公告)号：US08242822B2
公开(公告)日：2012-08-14
申请号：US13400967
申请日：2012-02-21
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

9. 发明申请

US20110291730A1 OPEN LOOP TYPE DELAY LOCKED LOOP AND METHOD FOR OPERATING THE SAME 失效
标题翻译：开环型延迟锁定环及其操作方法
公开(公告)号：US20110291730A1
公开(公告)日：2011-12-01
申请号：US12832549
申请日：2010-07-08
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K2005/00104
摘要： An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
摘要翻译：开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟响应代码值。

10. 发明申请

US20120154006A1 DUTY CYCLE CORRECTION CIRCUIT 有权
标题翻译：占空比校正电路
公开(公告)号：US20120154006A1
公开(公告)日：2012-06-21
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

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