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1. 发明申请

US20110237059A1 Non-volatile memory devices with multiple layers having band gap relationships among the layers 有权
标题翻译：具有层之间具有带隙关系的多层的非易失性存储器件
公开(公告)号：US20110237059A1
公开(公告)日：2011-09-29
申请号：US13067405
申请日：2011-05-31
申请人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
发明人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
IPC分类号： H01L21/28
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833
摘要： A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.
摘要翻译：非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。第一隧道绝缘层和第二隧道绝缘层可以顺序堆叠在半导体衬底上。第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

2. 发明授权

US08460999B2 Non-volatile memory devices with multiple layers having band gap relationships among the layers 有权
标题翻译：具有层之间具有带隙关系的多层的非易失性存储器件
公开(公告)号：US08460999B2
公开(公告)日：2013-06-11
申请号：US13067405
申请日：2011-05-31
申请人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
发明人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833
摘要： A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.
摘要翻译：非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。第一隧道绝缘层和第二隧道绝缘层可以顺序堆叠在半导体衬底上。第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

3. 发明授权

US07973355B2 Nonvolatile memory devices with multiple layers having band gap relationships among the layers 有权
标题翻译：具有层之间具有带隙关系的多层的非易失性存储器件
公开(公告)号：US07973355B2
公开(公告)日：2011-07-05
申请号：US12216945
申请日：2008-07-14
申请人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
发明人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833
摘要： A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.
摘要翻译：非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。第一隧道绝缘层和第二隧道绝缘层可以顺序堆叠在半导体衬底上。第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

4. 发明申请

US20090014781A1 Nonvolatile memory devices and methods for fabricating nonvolatile memory devices 有权
标题翻译：用于制造非易失性存储器件的非易失存储器件和方法
公开(公告)号：US20090014781A1
公开(公告)日：2009-01-15
申请号：US12216945
申请日：2008-07-14
申请人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
发明人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833
摘要： A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.
摘要翻译：非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。第一隧道绝缘层和第二隧道绝缘层可以顺序地堆叠在半导体衬底上。第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

5. 发明申请

US20080308876A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080308876A1
公开(公告)日：2008-12-18
申请号：US12155969
申请日：2008-06-12
申请人： Hye-Lan Lee , Si-Young Choi , Sang-Bom Kang , Si-Hyung Lee , Sang-Jin Hyun
发明人： Hye-Lan Lee , Si-Young Choi , Sang-Bom Kang , Si-Hyung Lee , Sang-Jin Hyun
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/4958 , H01L21/823828 , H01L27/092 , H01L29/4966
摘要： A semiconductor device includes a first gate structure on a first region of a substrate, the first gate structure including sequentially formed a first insulating layer pattern, a first conductive layer pattern, and a first polysilicon layer pattern doped with first impurities of a first conductivity type, a first source/drain in the first region of the substrate doped with second impurities of a second conductivity type, a second gate structure on a second region of the substrate, the second gate structure including sequentially formed a second insulating layer pattern, a second conductive layer pattern, and a second polysilicon layer pattern doped with third impurities with the first conductivity type, and a second source/drain in the second region of the substrate doped with fourth impurities having a conductivity type opposite the second conductivity.
摘要翻译：半导体器件包括在衬底的第一区域上的第一栅极结构，第一栅极结构包括顺序地形成第一绝缘层图案，第一导电层图案和掺杂有第一导电类型的第一杂质的第一多晶硅层图案掺杂有第二导电类型的第二杂质的衬底的第一区域中的第一源极/漏极，在衬底的第二区域上的第二栅极结构，第二栅极结构依次形成第二绝缘层图案，第二栅极结构导电层图案和掺杂有第一导电类型的第三杂质的第二多晶硅层图案，以及掺杂有具有与第二导电性相反的导电类型的第四杂质的第二基底的第二源极/漏极。

6. 发明申请

US20140374840A1 SEMICONDUCTOR DEVICES USING MOS TRANSISTORS WITH NONUNIFORM GATE ELECTRODE STRUCTURES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：使用具有非共振栅极电极结构的MOS晶体管的半导体器件及其制造方法
公开(公告)号：US20140374840A1
公开(公告)日：2014-12-25
申请号：US14312109
申请日：2014-06-23
申请人： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
发明人： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
IPC分类号： H01L27/088
CPC分类号： H01L27/0886 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
摘要翻译：半导体器件包括衬底和衬底上的第一和第二栅电极。第一栅极电极包括第一栅极绝缘膜，该第一栅极绝缘膜具有在基板上的底部部分以及侧壁部分，其从底部延伸并远离基板限定具有第一宽度的第一沟槽和填充第一沟槽的第一功能膜。所述第二栅电极包括第二栅极绝缘膜，所述第二栅极绝缘膜具有在所述基板上的底部部分和从所述底部部分延伸的侧壁部分，所述侧壁部分限定具有不同于所述第一宽度的第二宽度的第二沟槽;第二功能膜，在第二沟槽中并且限定第三沟槽，以及第三沟槽中的金属区域。第一宽度可以小于第二宽度。

7. 发明申请

US20110180879A1 CMOS TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND SEMICONDUCTOR MODULE INCLUDING THE DEVICE 有权
标题翻译： CMOS晶体管，包括晶体管的半导体器件和包括器件的半导体器件
公开(公告)号：US20110180879A1
公开(公告)日：2011-07-28
申请号：US12972961
申请日：2010-12-20
申请人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L23/522 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/82385 , H01L21/823871 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L27/0811 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
摘要翻译：提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。半导体衬底的第一和第二区域可以具有不同的导电类型。第一和第二互连结构可以设置在半导体衬底上。第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。半导体器件可以设置在半导体模块中。

8. 发明申请

US20080164508A1 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US20080164508A1
公开(公告)日：2008-07-10
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

9. 发明授权

US09780183B2 Semiconductor devices having work function metal films and tuning materials 有权
公开(公告)号：US09780183B2
公开(公告)日：2017-10-03
申请号：US14989154
申请日：2016-01-06
申请人： Wan-Don Kim , Oh-Seong Kwon , Hoon-Joo Na , Hyeok-Jun Son , Jae-Yeol Song , Sung-Kee Han , Sang-Jin Hyun
发明人： Wan-Don Kim , Oh-Seong Kwon , Hoon-Joo Na , Hyeok-Jun Son , Jae-Yeol Song , Sung-Kee Han , Sang-Jin Hyun
IPC分类号： H01L29/49 , H01L27/088 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/4966 , H01L21/823431 , H01L21/82345 , H01L21/823462 , H01L27/0886 , H01L29/42364 , H01L29/4238
摘要： A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

10. 发明授权

US09287199B2 CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device 有权
标题翻译： CMOS晶体管，包括晶体管的半导体器件和包括该器件的半导体模块
公开(公告)号：US09287199B2
公开(公告)日：2016-03-15
申请号：US12972961
申请日：2010-12-20
申请人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L23/522 , H01L23/485 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L29/94
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/82385 , H01L21/823871 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L27/0811 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
摘要翻译：提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。半导体衬底的第一和第二区域可以具有不同的导电类型。第一和第二互连结构可以设置在半导体衬底上。第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。半导体器件可以设置在半导体模块中。

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