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1. 发明授权

US07920418B2 Nonvolatile memory devices and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US07920418B2
公开(公告)日：2011-04-05
申请号：US11972243
申请日：2008-01-10
申请人： Seung-Chul Lee , Keun-Ho Lee , Choong-Ho Lee , Byung-Yong Choi
发明人： Seung-Chul Lee , Keun-Ho Lee , Choong-Ho Lee , Byung-Yong Choi
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/3418 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.
摘要翻译：非易失性存储器件包括第一导电类型的半导体衬底，半导体衬底上的多个字线，多条字线包括第二导电类型的浮置栅极。地线选择线和串选择线设置在字线的相应侧上。第二导电类型的杂质区域位于与地选线相邻的第一字线的正下方。该器件还可以包括第二导电类型的第二杂质区域，位于与串选择线相邻的第二字线下方。在另外的实施例中，器件还可以包括在第一字线和第二字线之间的相应第三字线下方的第二导电类型的第三杂质区。还提供了形成这种装置的方法。

2. 发明申请

US20080164509A1 Nonvolatile Memory Devices and Methods of Forming the Same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20080164509A1
公开(公告)日：2008-07-10
申请号：US11972243
申请日：2008-01-10
申请人： Seung-Chul Lee , Keun-Ho Lee , Choong-Ho Lee , Byung-Yong Choi
发明人： Seung-Chul Lee , Keun-Ho Lee , Choong-Ho Lee , Byung-Yong Choi
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/3418 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.
摘要翻译：非易失性存储器件包括第一导电类型的半导体衬底，半导体衬底上的多个字线，多条字线包括第二导电类型的浮置栅极。地线选择线和串选择线设置在字线的相应侧上。第二导电类型的杂质区域位于与地选线相邻的第一字线的正下方。该器件还可以包括第二导电类型的第二杂质区域，位于与串选择线相邻的第二字线下方。在另外的实施例中，器件还可以包括在第一字线和第二字线之间的相应第三字线下方的第二导电类型的第三杂质区。还提供了形成这种装置的方法。

3. 发明授权

US07602633B2 Non-volatile memory device, method of manufacturing the same, and method of operating the same 有权
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US07602633B2
公开(公告)日：2009-10-13
申请号：US11946737
申请日：2007-11-28
申请人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
IPC分类号： G11C11/00
CPC分类号： H01L29/685
摘要： A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.
摘要翻译：非易失性存储器件包括衬底，电阻图案，栅极介电层，栅极电极图案，第一杂质区域和第二杂质区域。基板有凹槽。凹槽中填充有电阻图案。电阻图案包括具有根据施加到其上的电压而可变的电阻的材料。栅极电介质层形成在基板上。栅极电极图案形成在栅极介电层上。在衬底中形成第一和第二杂质区。电阻图案的第一杂质区和第二杂质区接触侧表面。此外，电阻图案，第一杂质区域和第二杂质区域限定沟道区域。因此，非易失性存储器件可以使用电阻图案的可变电阻来存储数据，使得非易失性存储器件可以具有优异的操作特性。

4. 发明授权

US07465985B2 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07465985B2
公开(公告)日：2008-12-16
申请号：US11580086
申请日：2006-10-13
申请人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
IPC分类号： H01L21/334
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
摘要翻译：提供了一种非易失性存储器件及其形成方法。非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

5. 发明授权

US07419859B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07419859B2
公开(公告)日：2008-09-02
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

6. 发明申请

US20070048934A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US20070048934A1
公开(公告)日：2007-03-01
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

7. 发明授权

US07915138B2 Methods of manufacturing non-volatile memory devices 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07915138B2
公开(公告)日：2011-03-29
申请号：US12485577
申请日：2009-06-16
申请人： Hye-Jin Cho , Kyu-Charn Park , Choong-Ho Lee , Byung-Yong Choi
发明人： Hye-Jin Cho , Kyu-Charn Park , Choong-Ho Lee , Byung-Yong Choi
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.
摘要翻译：在制造非易失性存储器件的方法中，在衬底上形成导电结构。导电结构包括隧道氧化物图案，第一导电图案，衬垫氧化物图案和硬掩模图案。使用导电结构作为蚀刻掩模在衬底上形成沟槽。在沟槽的内壁和隧道氧化物图案的侧壁和第一导电图案上形成内部氧化物层。内部氧化物层被固化，从而在内部氧化物层上形成氮化硅层。在沟槽中形成器件隔离图案，并且从衬底去除硬掩模图案和衬垫氧化物图案。在基板上形成电介质层和第二导电图案。因此，氮化硅层防止氢（H）原子泄漏到器件隔离图案中。

8. 发明授权

US07883929B2 Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers 有权
标题翻译：通过将金属离子注入可变电阻层的晶界来制造非易失性存储器件的方法
公开(公告)号：US07883929B2
公开(公告)日：2011-02-08
申请号：US12035169
申请日：2008-02-21
申请人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
IPC分类号： H01L31/00
CPC分类号： H01L45/165 , H01L27/2436 , H01L45/085 , H01L45/1206 , H01L45/1226 , H01L45/146
摘要： Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.
摘要翻译：通过在集成电路基板上形成可变电阻层来制造集成电路非易失性存储器件。可变电阻层包括限定晶粒之间的晶界的晶粒。沿着至少一些晶界形成导电丝。电极形成在可变电阻层上。可以通过将导电离子注入至少一些晶界来形成导电细丝。此外，可变电阻层可以是金属的可变电阻氧化物，并且导电丝可以是金属。还公开了相关设备。

9. 发明授权

US07329580B2 Method of fabricating a semiconductor device having self-aligned floating gate and related device 有权
标题翻译：制造具有自对准浮动栅极和相关器件的半导体器件的方法
公开(公告)号：US07329580B2
公开(公告)日：2008-02-12
申请号：US11425205
申请日：2006-06-20
申请人： Byung-Yong Choi , Choong-Ho Lee , Tae-Yong Kim , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Tae-Yong Kim , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.
摘要翻译：提供了诸如具有自对准浮动栅极的闪速存储器件及其制造方法的半导体器件。该器件的一个实施例包括在半导体衬底中形成限定翅片体的隔离层。翅片本体具有突出在隔离层上方的部分。在隔离层上形成牺牲图案。牺牲图案具有与翅片体的突出部分自对准的开口。突出的翅片体露出开口。形成绝缘浮栅图形以填充开口。然后去除牺牲图案。形成覆盖浮栅图案的栅极间介电层。在栅极间电介质层上形成控制栅极导电层。对控制栅极导电层，栅极间电介质层和浮置栅极图案进行图案化以形成跨越鳍体的控制栅电极以及插在控制栅电极和鳍体之间的绝缘浮栅。

10. 发明授权

US07807517B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07807517B2
公开(公告)日：2010-10-05
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

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