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1. 发明申请

US20090051030A1 SEMICONDUCTOR PACKAGE WITH PAD PARTS ELECTRICALLY CONNECTED TO BONDING PADS THROUGH RE-DISTRIBUTION LAYERS 有权
标题翻译：半导体封装与电路连接到通过重新分配层连接的焊盘
公开(公告)号：US20090051030A1
公开(公告)日：2009-02-26
申请号：US11856266
申请日：2007-09-17
申请人： Seung Taek YANG , Shin Young PARK
发明人： Seung Taek YANG , Shin Young PARK
IPC分类号： H01L23/52
CPC分类号： H01L23/3114 , H01L23/481 , H01L23/525 , H01L24/06 , H01L24/12 , H01L2224/02319 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/06136 , H01L2224/16 , H01L2224/94 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/19041 , H01L2224/03 , H01L2224/11
摘要： The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards.
摘要翻译：半导体封装包括：具有多个相邻布置或整体形成的半导体芯片的半导体芯片模块，每个半导体芯片具有焊盘组和将包括在第一焊盘组中的每个焊盘电连接到第二焊盘组中的对应焊盘的连接构件焊盘组。在本发明中，可以在半导体芯片模块的外侧形成焊盘部件，以符合JEDEC的标准。这些焊盘部分然后通过再分配层连接到半导体芯片焊盘。即使在具有小于标准的焊盘的半导体芯片的情况下，半导体封装的焊盘部分也可符合JEDEC标准。

2. 发明申请

US20110042809A1 SEMICONDUCTOR PACKAGE WITH PAD PARTS ELECTRICALLY CONNECTED TO BONDING PADS THROUGH RE-DISTRIBUTION LAYERS 有权
标题翻译：半导体封装与电路连接到通过重新分配层连接的焊盘
公开(公告)号：US20110042809A1
公开(公告)日：2011-02-24
申请号：US12916907
申请日：2010-11-01
申请人： Seung Taek YANG , Shin Young PARK
发明人： Seung Taek YANG , Shin Young PARK
IPC分类号： H01L23/488
CPC分类号： H01L23/3114 , H01L23/481 , H01L23/525 , H01L24/06 , H01L24/12 , H01L2224/02319 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/06136 , H01L2224/16 , H01L2224/94 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/19041 , H01L2224/03 , H01L2224/11
摘要： The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards.
摘要翻译：半导体封装包括：具有多个相邻布置或整体形成的半导体芯片的半导体芯片模块，每个半导体芯片具有焊盘组和将包括在第一焊盘组中的每个焊盘电连接到第二焊盘组中的对应焊盘的连接构件焊盘组。在本发明中，可以在半导体芯片模块的外侧形成焊盘部件，以符合JEDEC的标准。这些焊盘部分然后通过再分配层连接到半导体芯片焊盘。即使在具有小于标准的焊盘的半导体芯片的情况下，半导体封装的焊盘部分也可符合JEDEC标准。

3. 发明申请

US20120299199A1 STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE 审中-公开
公开(公告)号：US20120299199A1
公开(公告)日：2012-11-29
申请号：US13569562
申请日：2012-08-08
申请人： Jong Hoon KIM , Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Tae Min KANG
发明人： Jong Hoon KIM , Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Tae Min KANG
IPC分类号： H01L23/488
CPC分类号： H01L25/0652 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L24/19 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2221/68345 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32145 , H01L2224/73217 , H01L2224/73267 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/06562 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/014 , H01L2924/12044 , H01L2924/15311 , H01L2924/15788 , H01L2924/18161 , H01L2924/18162 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/83005
摘要： A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

4. 发明申请

US20090026591A1 SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：适用于高速数据处理和损坏防护包装盒的半导体封装及其制造方法
公开(公告)号：US20090026591A1
公开(公告)日：2009-01-29
申请号：US11854067
申请日：2007-09-12
申请人： Seung Hyun LEE , Seung Taek YANG
发明人： Seung Hyun LEE , Seung Taek YANG
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/525 , H01L24/13 , H01L24/81 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/05553 , H01L2224/13 , H01L2224/13099 , H01L2224/16105 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , Y10S438/977 , H01L2924/00
摘要： A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball.
摘要翻译：半导体封装包括设置有具有接合焊盘的第一表面的半导体芯片，与第一表面相对的第二表面和侧表面; 与所述接合焊盘连接并沿着所述第一表面从所述接合焊盘延伸到与所述第二表面相交的所述侧表面的端部的第一再分布图案; 以及设置在所述第一再分布图案上并且从所述侧表面延伸到所述第一表面的第二再分配图案。在本发明的一个实施例中，其中与焊盘连接的第一再分布图案形成在半导体芯片之上，并且第二再分配图案形成在第一再分配图案之上，其能够减小用于信号传输的长度，因为第二再分配模式用作外部连接终端。由于半导体封装没有单独的焊球而连接到衬底，所以它也能够高速处理数据以及保护具有弱脆性的半导体芯片。

5. 发明申请

US20120171803A1 REVERSE IMAGE SENSOR MODULE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：反向图像传感器模块及其制造方法
公开(公告)号：US20120171803A1
公开(公告)日：2012-07-05
申请号：US13412821
申请日：2012-03-06
申请人： Seung Taek YANG
发明人： Seung Taek YANG
IPC分类号： H01L31/18
CPC分类号： H01L27/14645 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/1469
摘要： A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer.
摘要翻译：反向图像传感器模块包括第一和第二半导体芯片，以及第一和第二绝缘层。第一半导体芯片包括具有第一表面和背离第一表面的第二表面的第一半导体芯片本体，设置在第一表面上的光电二极管和布置在第二表面上并具有电连接到光电二极管的布线层的布线层以及电连接到布线的接合焊盘。第二半导体芯片包括具有面向布线层的第三表面的第二半导体芯片本体，以及与焊盘电连接并穿过第二半导体芯片主体的通孔。第一绝缘层设置在布线层上，第二绝缘层设置在与第一绝缘层相对的第二半导体芯片主体的第三表面上，并与第一绝缘层接合。

6. 发明申请

US20110121420A1 REVERSE IMAGE SENSOR MODULE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：反向图像传感器模块及其制造方法
公开(公告)号：US20110121420A1
公开(公告)日：2011-05-26
申请号：US12647648
申请日：2009-12-28
申请人： Seung Taek YANG
发明人： Seung Taek YANG
IPC分类号： H01L31/14 , H01L31/18 , H01L31/0232
CPC分类号： H01L27/14645 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/1469
摘要： A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer.
摘要翻译：反向图像传感器模块包括第一和第二半导体芯片，以及第一和第二绝缘层。第一半导体芯片包括具有第一表面和背离第一表面的第二表面的第一半导体芯片本体，设置在第一表面上的光电二极管和布置在第二表面上并具有电连接到光电二极管的布线层的布线层以及电连接到布线的接合焊盘。第二半导体芯片包括具有面向布线层的第三表面的第二半导体芯片本体，以及与焊盘电连接并穿过第二半导体芯片主体的通孔。第一绝缘层设置在布线层上，第二绝缘层设置在与第一绝缘层相对的第二半导体芯片主体的第三表面上，并与第一绝缘层接合。

7. 发明申请

US20090121326A1 SEMICONDUCTOR PACKAGE MODULE 有权
标题翻译：半导体封装模块
公开(公告)号：US20090121326A1
公开(公告)日：2009-05-14
申请号：US11953967
申请日：2007-12-11
申请人： Jong Hoon KIM , Min Suk SUH , Seong Cheol KIM , Seung Taek YANG , Seung Hyun LEE
发明人： Jong Hoon KIM , Min Suk SUH , Seong Cheol KIM , Seung Taek YANG , Seung Hyun LEE
IPC分类号： H01L23/495 , H01L23/538
CPC分类号： H05K1/141 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73253 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H05K1/021 , H05K1/182 , H05K1/183 , H05K3/0061 , H05K2201/10371 , H05K2201/10545 , H05K2201/10674 , H05K2203/1572
摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.
摘要翻译：一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

8. 发明申请

US20080001283A1 STACK PACKAGE WITH VERTICALLY FORMED HEAT SINK 失效
标题翻译：堆叠包装与垂直形成的散热器
公开(公告)号：US20080001283A1
公开(公告)日：2008-01-03
申请号：US11679268
申请日：2007-02-27
申请人： Ha Na LEE , Seung Taek YANG
发明人： Ha Na LEE , Seung Taek YANG
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L23/367 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73253 , H01L2224/9202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stack package includes a base substrate having connection pads on an upper surface thereof and ball lands on a lower surface thereof; at least two semiconductor chips stacked by intervening a spacer on the base substrate and defined with through-holes for electrical connections on positions corresponding to the connection pads; electrical connection members for electrically connecting the stacked semiconductor chips and the base substrate to each other; a pair of heat sinks formed such that they contact the side surfaces of the stacked semiconductor chips and extend in a direction perpendicular to the base substrate; and outside connection terminals attached to the ball lands located on the lower surface of the base substrate.
摘要翻译：堆叠封装包括在其上表面上具有连接焊盘的基底基板，并且在其下表面上具有焊盘; 至少两个半导体芯片通过在基底衬底上插入间隔物并且与对应于连接焊盘的位置上的用于电气连接的通孔间隔开来堆叠; 用于将堆叠的半导体芯片和基底基板彼此电连接的电连接构件; 一对散热片形成为使得它们接触堆叠的半导体芯片的侧表面并且在垂直于基底基板的方向上延伸; 以及附接到位于基底基板的下表面上的球接头的外部连接端子。

9. 发明申请

US20110287584A1 SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有侧壁的半导体封装及其制造方法
公开(公告)号：US20110287584A1
公开(公告)日：2011-11-24
申请号：US13197249
申请日：2011-08-03
申请人： Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Jong Hoon KIM
发明人： Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Jong Hoon KIM
IPC分类号： H01L21/78
CPC分类号： H01L23/4334 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/525 , H01L24/19 , H01L2221/68345 , H01L2221/68359 , H01L2224/04105 , H01L2224/20 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.
摘要翻译：半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面。在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。

10. 发明申请

US20110233795A1 STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE 审中-公开
标题翻译：具有减小尺寸的堆叠式水平包装
公开(公告)号：US20110233795A1
公开(公告)日：2011-09-29
申请号：US13158813
申请日：2011-06-13
申请人： Jong Hoon KIM , Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Tae Min KANG
发明人： Jong Hoon KIM , Min Suk SUH , Seung Taek YANG , Seung Hyun LEE , Tae Min KANG
IPC分类号： H01L23/488
CPC分类号： H01L25/0652 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L24/19 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2221/68345 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32145 , H01L2224/73217 , H01L2224/73267 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/06562 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/014 , H01L2924/12044 , H01L2924/15311 , H01L2924/15788 , H01L2924/18161 , H01L2924/18162 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/83005
摘要： A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.
摘要翻译：堆叠的晶片级封装包括具有第一焊盘的第一半导体芯片和具有第二焊盘的第二半导体芯片。半导体芯片的两个接合焊盘面向相同的方向。第二半导体芯片与第一半导体芯片平行设置。第三半导体芯片设置在用作支撑衬底的第一和第二半导体芯片上。第三半导体芯片具有在附接时在第一和第二半导体芯片之间露出的第三焊盘。最后，再分布结构电连接到第一，第二和第三键合焊盘。

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