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1. 发明申请

US20070168818A1 SEMICONDUCTOR TEST DEVICE WITH HEATING CIRCUIT 有权
标题翻译：具有加热电路的半导体测试装置
公开(公告)号：US20070168818A1
公开(公告)日：2007-07-19
申请号：US11673714
申请日：2007-02-12
申请人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant , Lisa Mullin
发明人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant , Lisa Mullin
IPC分类号： G01R31/30 , G06F11/00
CPC分类号： G01R31/2877 , G01R31/2856
摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
摘要翻译：半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

2. 发明申请

US20060066335A1 Semiconductor test device with heating circuit 审中-公开
标题翻译：带加热电路的半导体测试装置
公开(公告)号：US20060066335A1
公开(公告)日：2006-03-30
申请号：US10952453
申请日：2004-09-28
申请人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant , Lisa Mullin
发明人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant , Lisa Mullin
IPC分类号： G01R31/02
CPC分类号： G01R31/2877 , G01R31/2856
摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
摘要翻译：半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

3. 发明申请

US20060192584A1 Test semiconductor device and method for determining Joule heating effects in such a device 有权
标题翻译：测试这种器件中的焦耳加热效应的半导体器件和方法
公开(公告)号：US20060192584A1
公开(公告)日：2006-08-31
申请号：US11403750
申请日：2006-04-13
申请人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant
发明人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
摘要翻译：提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15 6）。测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。电阻率变化表示由于加热效应引起的温度变化。

4. 发明申请

US20060066337A1 Test semiconductor device and method for determining Joule heating effects in such a device 有权
公开(公告)号：US20060066337A1
公开(公告)日：2006-03-30
申请号：US10953292
申请日：2004-09-29
申请人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant
发明人： Seung Kang , Subramanian Karthikeyan , Sailesh Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

5. 发明授权

US06309900B1 Test structures for testing planarization systems and methods for using same 有权
标题翻译：用于测试平面化系统的测试结构及其使用方法
公开(公告)号：US06309900B1
公开(公告)日：2001-10-30
申请号：US09480387
申请日：2000-01-11
申请人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
发明人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.
摘要翻译：公开了用于系统中的测试结构以及用于测试在半导体器件和集成电路的制造中使用的平面化系统的有效性的相关方法。创建测试结构的方法利用传统的半导体制造技术，但是对测试结构的每个层使用基本相似的材料，例如氧化物。由于测试结构包括基本上相同材料的层，所以通过光学测量工具可以获得测试结构的厚度的可靠的均匀测量。然后可以将这些测量结果分析并显示在表格报告或多维图中，以判断平面化系统的有效性。

6. 发明授权

US07005375B2 Method to avoid copper contamination of a via or dual damascene structure 有权
标题翻译：避免通孔或双镶嵌结构铜污染的方法
公开(公告)号：US07005375B2
公开(公告)日：2006-02-28
申请号：US10260727
申请日：2002-09-30
申请人： Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76814
摘要： A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.
摘要翻译：防止互连金属扩散到周围电介质材料中的方法。在介电区域的开口中形成金属互连之前，清洁下面的金属表面，在该金属表面期间，金属可以沉积在开口的侧壁上。这种金属可以扩散到电介质中并引起漏电流。为了防止金属沉积到侧壁上，在金属表面清洁步骤之前，将阻挡层沉积到开口中并溅射到侧壁上。

7. 发明授权

US07804291B2 Semiconductor test device with heating circuit 有权
标题翻译：带加热电路的半导体测试装置
公开(公告)号：US07804291B2
公开(公告)日：2010-09-28
申请号：US11673714
申请日：2007-02-12
申请人： Seung H. Kang , Lisa E. Mullin , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Lisa E. Mullin , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/00 , G01R31/319 , G01R31/28
CPC分类号： G01R31/2877 , G01R31/2856
摘要： A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.
摘要翻译：半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

8. 发明授权

US07388395B2 Test semiconductor device and method for determining Joule heating effects in such a device 有权
标题翻译：测试这种器件中的焦耳加热效应的半导体器件和方法
公开(公告)号：US07388395B2
公开(公告)日：2008-06-17
申请号：US11403750
申请日：2006-04-13
申请人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
摘要翻译：提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15 6）。测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。电阻率变化表示由于加热效应引起的温度变化。

9. 发明授权

US07301107B2 Semiconductor device having reduced intra-level and inter-level capacitance 有权
标题翻译：具有降低的电平和电平间电容的半导体器件
公开(公告)号：US07301107B2
公开(公告)日：2007-11-27
申请号：US10694611
申请日：2003-10-27
申请人： Subramanian Karthikeyan , Sailesh Mansinh Merchant
发明人： Subramanian Karthikeyan , Sailesh Mansinh Merchant
IPC分类号： H05K1/11
CPC分类号： H01L23/5222 , H01L21/565 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/49575 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
摘要翻译：设计用于降低层间和层间电容的半导体器件的互连结构，并且包括下金属层和上金属层以及介于金属层之间的绝缘层。下金属层和上金属层中的每一个包括间隔开并在低k电介质材料内延伸的多条导线。多个金属填充的通孔将下金属层的导线与上金属层的导电线互连。绝缘层还包括设置在相邻的金属填充通孔之间的低k电介质材料。已经在上下金属层的导电线之间的低k电介质材料中蚀刻的开口和金属填充的通孔，在开口内沉积超低k材料。超低k和低d介电材料的集成降低了结构的总体电容以增强性能。

10. 发明授权

US07067419B2 Mask layer and dual damascene interconnect structure in a semiconductor device 失效
公开(公告)号：US07067419B2
公开(公告)日：2006-06-27
申请号：US10721126
申请日：2003-11-25
申请人： Robert Y S Huang , Scott Jessen , Subramanian Karthikeyan , Joshua Jia Li , Isaiah O. Oladeji , Kurt George Steiner , Joseph Ashley Taylor
发明人： Robert Y S Huang , Scott Jessen , Subramanian Karthikeyan , Joshua Jia Li , Isaiah O. Oladeji , Kurt George Steiner , Joseph Ashley Taylor
IPC分类号： H01L21/467
CPC分类号： H01L21/76811 , H01L21/76813
摘要： A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

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