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1. 发明申请

US20090284881A1 PACKAGE LEVEL ESD PROTECTION AND METHOD THEREFOR 有权
标题翻译：包装级ESD保护及其方法
公开(公告)号：US20090284881A1
公开(公告)日：2009-11-19
申请号：US12121608
申请日：2008-05-15
申请人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
发明人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
IPC分类号： H02H9/04 , H01L21/768
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.
摘要翻译：半导体封装包括能够耦合到第一导电触点和第二导电触点的静电放电导轨，在静电放电导轨和第一导电触点之间的电压触发材料的第一部分; 以及所述电压触发材料在所述静电放电导轨和所述第二导电触点之间的第二部分。第一和第二导电触点可以耦合到相同的半导体器件或不同的半导体器件。

2. 发明授权

US08059380B2 Package level ESD protection and method therefor 有权
标题翻译：封装级ESD保护及其方法
公开(公告)号：US08059380B2
公开(公告)日：2011-11-15
申请号：US12121608
申请日：2008-05-15
申请人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
发明人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
IPC分类号： H02H1/00
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.
摘要翻译：半导体封装包括能够耦合到第一导电触点和第二导电触点的静电放电导轨，在静电放电导轨和第一导电触点之间的电压触发材料的第一部分; 以及所述电压触发材料在所述静电放电导轨和所述第二导电触点之间的第二部分。第一和第二导电触点可以耦合到相同的半导体器件或不同的半导体器件。

3. 发明申请

US20090310266A1 METHOD AND CIRCUIT FOR eFUSE PROTECTION 有权
标题翻译：电子保护的方法和电路
公开(公告)号：US20090310266A1
公开(公告)日：2009-12-17
申请号：US12139106
申请日：2008-06-13
申请人： Melanie Etherton , Michael G. Khazhinsky , Eyal Melamed-Kohen , Valery Neiman
发明人： Melanie Etherton , Michael G. Khazhinsky , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： H02H9/00 , H01H85/00
CPC分类号： G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.
摘要翻译： eFuse（电子熔断器）电路具有用于确定在集成电路的电路板处是否发生ESD（静电放电）事件的第一检测器，并响应于此提供ESD触发信号。第二检测器检测第一电源电压的存在并提供指示第一电源电压的存在的上电信号。当不发生ESD事件检测时，保险丝被允许可编程，同时检测到通电信号的存在。当检测到ESD事件或没有通电信号时，不允许对熔丝进行编程。因此，保险丝阵列可以防止意外编程从ESD事件或加电集成电路。

4. 发明申请

US20150349522A1 ELECTROSTATIC DISCHARGE PROTECTION SYSTEM 有权
标题翻译：静电放电保护系统
公开(公告)号：US20150349522A1
公开(公告)日：2015-12-03
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译：集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。多个I / O单元的第一组沿着集成电路的管芯边缘布置。多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分第一组和第二组的邻接I / O单元。集成电路包括ESD钳位和触发电路。

5. 发明授权

US07589945B2 Distributed electrostatic discharge protection circuit with varying clamp size 有权
标题翻译：具有不同钳位尺寸的分布式静电放电保护电路
公开(公告)号：US07589945B2
公开(公告)日：2009-09-15
申请号：US11513638
申请日：2006-08-31
申请人： James W. Miller , Melanie Etherton , Michael G. Khazhinsky , Michael Stockinger
发明人： James W. Miller , Melanie Etherton , Michael G. Khazhinsky , Michael Stockinger
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译：集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。第一ESD钳位晶体管器件具有第一通道宽度。集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。

6. 发明授权

US09064938B2 I/O cell ESD system 有权
标题翻译： I / O单元ESD系统
公开(公告)号：US09064938B2
公开(公告)日：2015-06-23
申请号：US13905275
申请日：2013-05-30
申请人： Melanie Etherton , Alexey Gilgur , James W. Miller , Jonathan M. Phillippe , Robert S. Ruth
发明人： Melanie Etherton , Alexey Gilgur , James W. Miller , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H01L21/768 , H01L23/535 , H01L27/02
CPC分类号： H01L21/76895 , H01L27/0296 , H01L2224/05554
摘要： An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.
摘要翻译：一种包括ESD网络的集成电路，其包括位于多个I / O单元的ESD子区域中的部分，其中ESD子区域布置成穿过多个I / O单元的行。 ESD网络包括ESD钳位单元和ESD触发电路单元，其中网络的一部分位于该行中。在一些示例中，行包括ESD触发电路单元，其具有一个I / O单元的一个ESD子区域的一个子区域中的一部分，以及另一个I / O单元的第二ESD子区域中的第二部分。本文还描述了一种用于产生具有ESD网络的集成电路布局的方法。

7. 发明授权

US09478529B2 Electrostatic discharge protection system 有权
标题翻译：静电放电保护系统
公开(公告)号：US09478529B2
公开(公告)日：2016-10-25
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H3/22 , H01L27/02 , H05K9/00 , H02H9/04 , H02H3/20 , H01L23/00
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译：集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。多个I / O单元的第一组沿着集成电路的管芯边缘布置。多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。对于第一组中的每个I / O单元，第一功率总线的部分物理地连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分第一组和第二组的邻接I / O单元。集成电路包括ESD钳位和触发电路。

8. 发明授权

US08009397B2 Method and circuit for eFuse protection 有权
标题翻译： eFuse保护的方法和电路
公开(公告)号：US08009397B2
公开(公告)日：2011-08-30
申请号：US12139106
申请日：2008-06-13
申请人： Melanie Etherton , Michael G. Khazhinsky , Eyal Melamed-Kohen , Valery Neiman
发明人： Melanie Etherton , Michael G. Khazhinsky , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： H02H9/00
CPC分类号： G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.
摘要翻译： eFuse（电子熔断器）电路具有用于确定在集成电路的电路板处是否发生ESD（静电放电）事件的第一检测器，并响应于此提供ESD触发信号。第二检测器检测第一电源电压的存在并提供指示第一电源电压的存在的上电信号。当不发生ESD事件检测时，保险丝被允许可编程，同时检测到通电信号的存在。当检测到ESD事件或没有通电信号时，不允许对熔丝进行编程。因此，保险丝阵列可以防止意外编程从ESD事件或加电集成电路。

9. 发明申请

US20080062596A1 Distributed electrostatic discharge protection circuit with varying clamp size 有权
标题翻译：具有不同钳位尺寸的分布式静电放电保护电路
公开(公告)号：US20080062596A1
公开(公告)日：2008-03-13
申请号：US11513638
申请日：2006-08-31
申请人： James W. Miller , Melanie Etherton , Michael G. Khazhinsky , Michael Stockinger
发明人： James W. Miller , Melanie Etherton , Michael G. Khazhinsky , Michael Stockinger
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译：集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。第一ESD钳位晶体管器件具有第一通道宽度。集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。

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