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1. 发明授权

US5510645A Semiconductor structure having an air region and method of forming the semiconductor structure 失效
标题翻译：具有空气区域的半导体结构和形成半导体结构的方法
公开(公告)号：US5510645A
公开(公告)日：1996-04-23
申请号：US383908
申请日：1995-01-17
申请人： Jon T. Fitch , Papu Maniar , Keith E. Witek , Jerry Gelatos , Reza Moazzami , Sergio A. Ajuria
发明人： Jon T. Fitch , Papu Maniar , Keith E. Witek , Jerry Gelatos , Reza Moazzami , Sergio A. Ajuria
IPC分类号： G01P15/08 , H01L21/768 , H01L23/482 , H01L29/00
CPC分类号： G01P15/0802 , H01L21/7682 , H01L23/4821 , H01L2924/0002 , Y10S148/073
摘要： A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.
摘要翻译：一种用于形成覆盖在基底层（12）上的空气区域或空气桥的方法。空气区域（20a，20b，28a和48）形成在基底层（12）上，以提供相邻导电层的改进的介电隔离，提供空气隔离的导电互连和/或形成许多其它微结构或微器件。通过选择性地去除牺牲隔离物（16a和16b）或通过选择性地除去牺牲层（28,40）来形成空气区域（20a，20b，28a和48）。空气区域（20a，20b，28a和48）通过选择性生长过程或通过非保形沉积技术被密封，封闭或隔离。空气区域（20a，20b，28a和48）可以在任何压力，气体浓度或加工条件（即温度等）下形成。空气区域（20a，20b，28a和48）可以形成在集成电路内的任何水平处。

2. 发明授权

US09548266B2 Semiconductor package with embedded capacitor and methods of manufacturing same 有权
标题翻译：具有嵌入式电容器的半导体封装及其制造方法相同
公开(公告)号：US09548266B2
公开(公告)日：2017-01-17
申请号：US14469645
申请日：2014-08-27
申请人： Sergio A. Ajuria , Phuc M. Nyugen , Douglas M. Reber
发明人： Sergio A. Ajuria , Phuc M. Nyugen , Douglas M. Reber
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L28/60 , H01L23/3114 , H01L23/4824 , H01L23/485 , H01L23/5223 , H01L24/02 , H01L24/12 , H01L24/13 , H01L2224/02331 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
摘要翻译：描述了具有嵌入式电容器的半导体封装和相应的制造方法。具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。

3. 发明申请

US20160064294A1 SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS 有权
标题翻译：用于形成粘结垫和密封圈的半导体制造
公开(公告)号：US20160064294A1
公开(公告)日：2016-03-03
申请号：US14470383
申请日：2014-08-27
申请人： DOUGLAS M. REBER , Sergio A. Ajuria , Phuc M. Nguyen
发明人： DOUGLAS M. REBER , Sergio A. Ajuria , Phuc M. Nguyen
IPC分类号： H01L21/66 , H01L21/48 , H01L23/00
CPC分类号： H01L21/4846 , H01L22/34 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0237 , H01L2224/02371 , H01L2224/0239 , H01L2224/039 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05023 , H01L2224/05548 , H01L2224/05568 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13147 , H01L2224/81203 , H01L2224/85048 , H01L2224/85205 , H01L2224/85207 , H01L2224/8581 , H01L2224/92 , H01L2224/9212 , H01L2224/94 , H01L2924/00014 , H01L2924/3512 , H01L2924/35121 , H01L2924/01013 , H01L2924/01029 , H01L2924/00012 , H01L2224/0231 , H01L2224/03 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.
摘要翻译：集成电路管芯包括第一接合焊盘，该第一接合焊盘在集成电路管芯的半导体衬底上的第一深度处具有多个堆叠层中的接合区域，其具有包围接合区域的侧壁，第一深度到多个堆积层的顶表面，并且具有在多个堆积层的顶表面的一部分上延伸的顶部。

4. 发明申请

US20150200146A1 Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes 审中-公开
标题翻译：半导体制造在标定车道内使用一次性测试电路
公开(公告)号：US20150200146A1
公开(公告)日：2015-07-16
申请号：US14153417
申请日：2014-01-13
申请人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
发明人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
IPC分类号： H01L21/66 , H01L23/00 , H01L23/29 , H01L23/10 , H01L21/78
CPC分类号： H01L22/34 , H01L21/78 , H01L22/32 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.
摘要翻译：公开了使用在划线中形成的一次性测试电路的半导体制造的实施例。制造步骤可以包括在半导体管芯内形成器件电路并在划线内形成测试电路。还形成一个或多个连接设备电路和测试电路块的电连接路线。此外，每个管芯可以连接到单个测试电路块，或者多个管芯可以共享公共测试电路块。测试后，电气连接路线被密封，并且当设备裸片被切割时，测试电路被丢弃。对于某些实施例，器件裸片的边缘被保护金属层封装，并且某些其它实施例包括保护性密封件，连接路线经过该保护密封件从划线中的测试电路块进入骰子。

5. 发明授权

US09134366B2 Method for forming a packaged semiconductor device 有权
标题翻译：用于形成封装的半导体器件的方法
公开(公告)号：US09134366B2
公开(公告)日：2015-09-15
申请号：US14011160
申请日：2013-08-27
申请人： Sergio A. Ajuria , Phuc M. Nguyen , Douglas M. Reber
发明人： Sergio A. Ajuria , Phuc M. Nguyen , Douglas M. Reber
IPC分类号： H01L21/66 , G01R31/28 , H01L23/522
CPC分类号： G01R31/2884 , G01R31/2896 , H01L22/32 , H01L23/5226 , H01L24/19 , H01L2224/13
摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.
摘要翻译：制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。将管芯载体分离以形成多个封装的半导体器件。在分离模具载体期间移除探针焊盘组。

6. 发明授权

US08059380B2 Package level ESD protection and method therefor 有权
标题翻译：封装级ESD保护及其方法
公开(公告)号：US08059380B2
公开(公告)日：2011-11-15
申请号：US12121608
申请日：2008-05-15
申请人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
发明人： Sergio A. Ajuria , Melanie Etherton , Marc A. Mangrum
IPC分类号： H02H1/00
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.
摘要翻译：半导体封装包括能够耦合到第一导电触点和第二导电触点的静电放电导轨，在静电放电导轨和第一导电触点之间的电压触发材料的第一部分; 以及所述电压触发材料在所述静电放电导轨和所述第二导电触点之间的第二部分。第一和第二导电触点可以耦合到相同的半导体器件或不同的半导体器件。

7. 发明授权

US5885870A Method for forming a semiconductor device having a nitrided oxide dielectric layer 失效
标题翻译：用于形成具有氮化氧化物介电层的半导体器件的方法
公开(公告)号：US5885870A
公开(公告)日：1999-03-23
申请号：US886927
申请日：1997-07-02
申请人： Bikas Maiti , Philip J. Tobin , Sergio A. Ajuria
发明人： Bikas Maiti , Philip J. Tobin , Sergio A. Ajuria
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28202 , H01L21/3144 , H01L21/31662 , H01L29/513 , H01L29/518 , H01L29/66825
摘要： In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.
摘要翻译：在一个实施例中，通过氧化半导体衬底（12）的第一部分以形成第一二氧化硅层（14）来形成具有改善的可靠性的非易失性存储器件。然后退火第一二氧化硅层（14），然后氧化氧化形成第二二氧化硅层（18）的第二部分硅衬底（在退火的二氧化硅层下面）。退火的二氧化硅层（16）和第二二氧化硅层（18）形成预氧化物层（20）。然后将预氧化物层（20）氮化以形成氮化氧化物介电层（22）。然后形成覆盖氮化氧化物介电层（22）的浮栅，其用作器件的隧道氧化物。用本发明方法形成的隧道氧化物不易受到应力诱发的泄漏的影响，因此，可以制造具有改善的数据保持和耐久性的装置。

8. 发明授权

US10553508B2 Semiconductor manufacturing using disposable test circuitry within scribe lanes 有权
公开(公告)号：US10553508B2
公开(公告)日：2020-02-04
申请号：US14153417
申请日：2014-01-13
申请人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
发明人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
IPC分类号： H01L21/66 , H01L21/78 , H01L23/00
摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

9. 发明申请

US20160064324A1 SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME 有权
标题翻译：具有嵌入式电容器的半导体封装及其制造方法
公开(公告)号：US20160064324A1
公开(公告)日：2016-03-03
申请号：US14469645
申请日：2014-08-27
申请人： Sergio A. Ajuria , Phuc M. Nyugen , Douglas M. Reber
发明人： Sergio A. Ajuria , Phuc M. Nyugen , Douglas M. Reber
IPC分类号： H01L23/522 , H01L21/283 , H01L49/02 , H01L21/78
CPC分类号： H01L28/60 , H01L23/3114 , H01L23/4824 , H01L23/485 , H01L23/5223 , H01L24/02 , H01L24/12 , H01L24/13 , H01L2224/02331 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
摘要翻译：描述了具有嵌入式电容器的半导体封装和相应的制造方法。具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。

10. 发明授权

US09601354B2 Semiconductor manufacturing for forming bond pads and seal rings 有权
公开(公告)号：US09601354B2
公开(公告)日：2017-03-21
申请号：US14470383
申请日：2014-08-27
申请人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
发明人： Douglas M. Reber , Sergio A. Ajuria , Phuc M. Nguyen
IPC分类号： H01L21/66 , H01L21/48 , H01L23/00 , H01L23/522 , H01L23/58
CPC分类号： H01L21/4846 , H01L22/34 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0237 , H01L2224/02371 , H01L2224/0239 , H01L2224/039 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05023 , H01L2224/05548 , H01L2224/05568 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13147 , H01L2224/81203 , H01L2224/85048 , H01L2224/85205 , H01L2224/85207 , H01L2224/8581 , H01L2224/92 , H01L2224/9212 , H01L2224/94 , H01L2924/00014 , H01L2924/3512 , H01L2924/35121 , H01L2924/01013 , H01L2924/01029 , H01L2924/00012 , H01L2224/0231 , H01L2224/03 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

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