专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060165204A1 Method and apparatus for multi-mode clock data recovery 失效
公开(公告)号：US20060165204A1
公开(公告)日：2006-07-27
申请号：US11040342
申请日：2005-01-21
申请人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
发明人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

2. 发明申请

US20060220681A1 Methods and apparatus to DC couple LVDS driver to CML levels 有权
标题翻译：将LVDS驱动程序直接耦合到CML级别的方法和设备
公开(公告)号：US20060220681A1
公开(公告)日：2006-10-05
申请号：US11098832
申请日：2005-04-04
申请人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
发明人： Wilson Wong , Tim Hoang , Sergey Shumarayev , Rakesh Patel , Simardeep Maangat
IPC分类号： H03K19/094
CPC分类号： H03K19/017545
摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.
摘要翻译：为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。此外，电阻下拉可以是可编程的。这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

3. 发明申请

US20070025436A1 High-speed data reception circuitry and methods 有权
标题翻译：高速数据接收电路和方法
公开(公告)号：US20070025436A1
公开(公告)日：2007-02-01
申请号：US11192539
申请日：2005-07-28
申请人： Sergey Shumarayev , Wilson Wong , Rakesh Patel
发明人： Sergey Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03573
摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.
摘要翻译：用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

4. 发明授权

US07132847B1 Programmable slew rate control for differential output 有权
标题翻译：差分输出的可编程压摆率控制
公开(公告)号：US07132847B1
公开(公告)日：2006-11-07
申请号：US10708303
申请日：2004-02-24
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H03K19/003
CPC分类号： H03K17/6872 , H03K17/164
摘要： A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.
摘要翻译：可编程技术用于控制差分输出缓冲器的转换速率。一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。具体应用是可编程逻辑集成电路的差分输出。

5. 发明授权

US07773668B1 Adaptive equalization methods and apparatus for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自适应均衡方法和装置
公开(公告)号：US07773668B1
公开(公告)日：2010-08-10
申请号：US10762864
申请日：2004-01-21
申请人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译：可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否（5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

6. 发明申请

US20090141787A1 ADAPTIVE EQUALIZATION METHODS AND APPARATUS 有权
标题翻译：自适应均衡方法和装置
公开(公告)号：US20090141787A1
公开(公告)日：2009-06-04
申请号：US12358459
申请日：2009-01-23
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H04L27/01
CPC分类号： H04L1/205 , H04B17/21 , H04B17/24 , H04B17/309 , H04L25/03006
摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
摘要翻译：系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

7. 发明申请

US20070140387A1 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US20070140387A1
公开(公告)日：2007-06-21
申请号：US11312181
申请日：2005-12-20
申请人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
发明人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
IPC分类号： H04L27/06
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

8. 发明申请

US20070041455A1 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US20070041455A1
公开(公告)日：2007-02-22
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H04L25/00
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

9. 发明申请

US20050237082A1 Integrated circuit output driver circuitry with programmable preemphasis 有权
公开(公告)号：US20050237082A1
公开(公告)日：2005-10-27
申请号：US11148046
申请日：2005-06-07
申请人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
发明人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K19/003
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

10. 发明授权

US08194724B1 Adaptive equalization methods and apparatus for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自适应均衡方法和装置
公开(公告)号：US08194724B1
公开(公告)日：2012-06-05
申请号：US12823783
申请日：2010-06-25
申请人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Simardeep Maangat , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03044 , H04L2025/03356 , H04L2025/03579 , H04L2025/03783
摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.
摘要翻译：可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否（5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式