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1. 发明授权

US09009390B2 Method for changing read parameter for improving read performance and apparatuses using the same 有权
标题翻译：用于改变读取参数以提高读取性能的方法和使用其的装置
公开(公告)号：US09009390B2
公开(公告)日：2015-04-14
申请号：US13238749
申请日：2011-09-21
申请人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
发明人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
IPC分类号： G06F13/00 , G06F13/28 , G11C16/02 , G11C16/06 , G11C29/42 , G11C16/00 , G11C11/56 , G11C16/34
CPC分类号： G11C16/02 , G06F13/00 , G11C11/5642 , G11C16/00 , G11C16/06 , G11C16/3418 , G11C16/349 , G11C29/42
摘要： A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.
摘要翻译：提供了包括非易失性存储器件和存储器控制器的存储器系统。当在第一次读取操作期间最初从非易失性存储器件输出的第一数据的读取操作成功时，存储器控制器可以在第二次读取期间改变用于读取存储在非易失性存储器件中的第二数据的读取电压操作。

2. 发明授权

US09864544B2 Methods of operating memory systems for sub-block erase operation 有权
公开(公告)号：US09864544B2
公开(公告)日：2018-01-09
申请号：US15001275
申请日：2016-01-20
申请人： Eun Chu Oh , Hong Rak Son , Jun Jin Kong , Seong Hyeog Choi
发明人： Eun Chu Oh , Hong Rak Son , Jun Jin Kong , Seong Hyeog Choi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/06
CPC分类号： G06F3/0652 , G06F3/0614 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F3/0679 , G06F3/0688
摘要： A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.

3. 发明授权

US08711618B2 Method for programming non-volatile memory device and apparatuses performing the method 有权
标题翻译：用于编程执行该方法的非易失性存储器件和装置的方法
公开(公告)号：US08711618B2
公开(公告)日：2014-04-29
申请号：US13190913
申请日：2011-07-26
申请人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
发明人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10
摘要： A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.
摘要翻译：一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

4. 发明授权

US08635509B2 Method of operating memory controller and memory system including the memory controller 失效
标题翻译：操作存储器控制器和存储器系统的方法，包括存储器控制器
公开(公告)号：US08635509B2
公开(公告)日：2014-01-21
申请号：US13612074
申请日：2012-09-12
申请人： Seong Hyeog Choi , Jun Jin Kong , Hong Rak Son
发明人： Seong Hyeog Choi , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1072 , G06F11/108 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： According to example embodiments, a method of controlling a memory controller includes executing an error correction code (ECC) on first page data that has been read from a non-volatile memory device using a first read voltage level, estimating a second read voltage level for reading the first page data using metadata of second page data when an uncorrectable error is detected in the first page data according to a result of executing the ECC.
摘要翻译：根据示例实施例，一种控制存储器控制器的方法包括：对使用第一读取电压电平从非易失性存储器件读取的第一页数据执行纠错码（ECC），估计第二读取电压电平根据执行ECC的结果在第一页数据中检测到不可校正的错误时，使用第二页数据的元数据读取第一页数据。

5. 发明申请

US20120020156A1 METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES PERFORMING THE METHOD 有权
标题翻译：编程非易失性存储器件的方法及其方法
公开(公告)号：US20120020156A1
公开(公告)日：2012-01-26
申请号：US13190913
申请日：2011-07-26
申请人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
发明人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10
摘要： A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.
摘要翻译：一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

6. 发明授权

US08004891B2 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US08004891B2
公开(公告)日：2011-08-23
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

7. 发明申请

US20100020620A1 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US20100020620A1
公开(公告)日：2010-01-28
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04 , G06F12/00
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

8. 发明授权

US08706953B2 Data storage device and method performing background operation with selected data compression 有权
标题翻译：数据存储设备和方法通过选择的数据压缩执行后台操作
公开(公告)号：US08706953B2
公开(公告)日：2014-04-22
申请号：US13096036
申请日：2011-04-28
申请人： Kyoung Lae Cho , Kwang Ho Kim , Jun Jin Kong , Jaehong Kim , Hong Rak Son
发明人： Kyoung Lae Cho , Kwang Ho Kim , Jun Jin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G06F12/02
CPC分类号： H03M7/30
摘要： A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.
摘要翻译：一种在数据存储装置的存储介质中存储数据的方法包括将输入数据存储在存储介质中，并从存储介质读取输入数据，并在数据存储装置的后台操作期间压缩读取的数据。

9. 发明授权

US08972775B2 Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit 有权
标题翻译：存储器件和管理存储器数据错误的方法，包括基于校正的误差位确定验证电压和改变阈值电压
公开(公告)号：US08972775B2
公开(公告)日：2015-03-03
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/07 , G11C16/10 , G06F11/10 , G11C11/56 , G11C16/34 , G11C29/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

10. 发明授权

US08508990B2 Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device 有权
标题翻译：非易失性存储器件，其操作方法以及具有非易失性存储器件的器件
公开(公告)号：US08508990B2
公开(公告)日：2013-08-13
申请号：US13071727
申请日：2011-03-25
申请人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
发明人： Kyoung Lae Cho , Hyuck-Sun Kwon , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454
摘要： A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.
摘要翻译：非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个多电平单元，每个多电平单元存储对应于第一组状态的多种状态之一的数据，以及控制电路。控制电路被配置为根据第一组验证电压电平的第一验证电压电平对与第一多电平单元中的多个状态中的一个状态相对应的数据，并且将第一多电平单元控制为根据第二组验证电压电平的第一验证电压电平，将其重新编程为第二组状态的多个状态之一。第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。

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