专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07330043B2 Semiconductor device and test method for the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US07330043B2
公开(公告)日：2008-02-12
申请号：US11079142
申请日：2005-03-15
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

2. 发明授权

US06885212B2 Semiconductor device and test method for the same 失效
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US06885212B2
公开(公告)日：2005-04-26
申请号：US10356489
申请日：2003-02-03
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/28 , G01R31/04 , G11C7/10 , H01L21/822 , H01L27/04 , G01R31/26
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

3. 发明申请

US20050156589A1 Semiconductor device and test method for the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US20050156589A1
公开(公告)日：2005-07-21
申请号：US11079142
申请日：2005-03-15
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/28 , G01R31/04 , G11C7/10 , H01L21/822 , H01L27/04 , G01R31/02
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

4. 发明授权

US5559741A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5559741A
公开(公告)日：1996-09-24
申请号：US366729
申请日：1994-12-30
申请人： Isaya Sobue
发明人： Isaya Sobue
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/70 , G11C29/44
摘要： In a semiconductor memory device with redundant configuration, a redundant address detection circuit is additionally provided between an I/O buffer and a read/write circuit coupled to a memory cell array. The detection circuit receives both a signal indicating the detection of redundancy from a redundant address setter and a signal instructing a test mode for the memory device, and selectively inverts the logic of data associated with the redundant cell. When the data is supplied to memory cells through the redundant address detection circuit under test mode conditions, only data involved in a redundant address is inverted in logic and is written into a redundant cell. Subsequently, a tester reads out the write data of all memory cells to produce a bit map indicating the address of the inverted data and allowing the tester to detect the address of redundant memory cells.
摘要翻译：在具有冗余配置的半导体存储器件中，冗余地址检测电路被附加地设置在I / O缓冲器和耦合到存储单元阵列的读/写电路之间。检测电路接收来自冗余地址设定器的指示冗余检测的信号和指示存储器件的测试模式的信号，并且选择性地反转与冗余单元相关联的数据的逻辑。当通过冗余地址检测电路在测试模式条件下将数据提供给存储单元时，仅冗余地址中涉及的数据在逻辑中反相并写入冗余单元。随后，测试者读出所有存储器单元的写入数据，以产生指示反相数据的地址的位图，并允许测试器检测冗余存储单元的地址。

5. 发明授权

US5508965A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5508965A
公开(公告)日：1996-04-16
申请号：US305722
申请日：1994-09-14
申请人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
发明人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
IPC分类号： G11C7/06 , G11C11/406 , G11C11/4091 , G11C7/02
CPC分类号： G11C11/406 , G11C11/4091 , G11C7/065
摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.
摘要翻译：公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

6. 发明授权

US5619465A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5619465A
公开(公告)日：1997-04-08
申请号：US584471
申请日：1996-01-11
申请人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
发明人： Hidenori Nomura , Kenji Nagai , Masami Nakashima , Hiroshi Yamamoto , Isaya Sobue
IPC分类号： G11C7/06 , G11C11/406 , G11C11/4091 , G11C7/02
CPC分类号： G11C11/406 , G11C11/4091 , G11C7/065
摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.
摘要翻译：公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式