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1. 发明授权

US07330043B2 Semiconductor device and test method for the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US07330043B2
公开(公告)日：2008-02-12
申请号：US11079142
申请日：2005-03-15
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

2. 发明授权

US08742786B2 Semiconductor device and operation monitoring method for semiconductor device 有权
标题翻译：半导体器件的半导体器件和操作监控方法
公开(公告)号：US08742786B2
公开(公告)日：2014-06-03
申请号：US12410157
申请日：2009-03-24
申请人： Kazufumi Komura , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
发明人： Kazufumi Komura , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
IPC分类号： G01R31/02
CPC分类号： G01R31/318555 , G01R31/318533 , G01R31/318552
摘要： A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
摘要翻译：一种半导体器件包括：监测器，包括耦合在第一电源线和第二电源线之间的第一元件和用于增加第一元件与第一电源线或第二电源线之间的负载值的负载;以及确定单元，其基于所述监视器的输出来确定所述第一元素的操作状态。

3. 发明授权

US5506808A Semiconductor memory device and method for reading data 失效
标题翻译：半导体存储器件和数据读取方法
公开(公告)号：US5506808A
公开(公告)日：1996-04-09
申请号：US305715
申请日：1994-09-14
申请人： Katsuyuki Yamada , Tohru Yasuda
发明人： Katsuyuki Yamada , Tohru Yasuda
IPC分类号： G11C7/10 , G11C11/419 , G11C7/00
CPC分类号： G11C7/1051 , G11C11/419
摘要： Disclosed is a data reading process as well as an improved semiconductor memory device. Input data supplied to the memory device is written in one of memory cells via a pair of bit lines when a write enable signal is active. After writing of the input data is completed, an equalizing circuit is activated to equalize the potential levels of bit lines used in data writing. An output circuit of the memory device is controlled such that the input data is forcibly output as output data from the memory device during the equalization immediately after writing of the input data is completed.
摘要翻译：公开了一种数据读取过程以及改进的半导体存储器件。当写使能信号有效时，提供给存储器件的输入数据通过一对位线写入存储单元之一。在输入数据写入完成之后，激活均衡电路以均衡数据写入中使用的位线的电位。控制存储器件的输出电路，使得输入数据在写入输入数据之后立即在均衡期间从存储器件强制输出作为输出数据输出。

4. 发明授权

US5433860A Process for treating waste washing water used for impregnation 失效
标题翻译：处理用于浸渍的废水清洗水的方法
公开(公告)号：US5433860A
公开(公告)日：1995-07-18
申请号：US122478
申请日：1994-01-12
申请人： Tohru Yasuda
发明人： Tohru Yasuda
IPC分类号： B01D61/14 , B01D61/16 , B08B3/14 , C02F1/44 , C10M175/06 , C23G1/36
CPC分类号： C02F1/444 , B01D61/145 , B01D61/147 , B01D61/16 , C10M175/06 , B01D2311/04
摘要： A process for treating waste washing water, which is only slightly affected by temperature, can dispense with any chemical, and wherein the quality of treated water is not affected by a change in the waste water concentration. The process comprises conducting impregnation with an impregnant having a composition comprising triethylene glycol dimethacrylate, 2-hydroxyethyl methacrylate, lauryl methacrylate, nonionic surfactant and azobisisobutyronitrile; separating the impregnant thereafter; washing the surface of the impregnated article with water; and treating the waste water by filtering the liquid having the above composition though a filter having a retained particle diameter of at most 20 .mu.m.
摘要翻译： PCT No.PCT / JP92 / 00380 Sec。 371日期：1994年1月12日 102（e）日期1994年1月12日PCT 1991年3月27日PCT公布。公开号WO92 / 17408 日期为1992年10月15日。处理仅受温度稍微影响的废水洗涤水的方法可以省去任何化学品，其中处理水的质量不受废水浓度变化的影响。该方法包括用具有三甘醇二甲基丙烯酸酯，甲基丙烯酸2-羟乙酯，甲基丙烯酸月桂酯，非离子表面活性剂和偶氮二异丁腈的组合物的浸渍剂进行浸渍; 此后分离浸渍剂; 用水清洗浸渍物品的表面; 并通过过滤具有上述组成的液体，并通过具有至多20μm的保留粒径的过滤器来处理废水。

5. 发明申请

US20050156589A1 Semiconductor device and test method for the same 有权
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US20050156589A1
公开(公告)日：2005-07-21
申请号：US11079142
申请日：2005-03-15
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/28 , G01R31/04 , G11C7/10 , H01L21/822 , H01L27/04 , G01R31/02
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

6. 发明授权

US06885212B2 Semiconductor device and test method for the same 失效
标题翻译：半导体器件及其测试方法相同
公开(公告)号：US06885212B2
公开(公告)日：2005-04-26
申请号：US10356489
申请日：2003-02-03
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
IPC分类号： G01R31/28 , G01R31/04 , G11C7/10 , H01L21/822 , H01L27/04 , G01R31/26
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译：多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

7. 发明申请

US20090243627A1 SEMICONDUCTOR DEVICE AND OPERATION MONITORING METHOD FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和操作监控方法
公开(公告)号：US20090243627A1
公开(公告)日：2009-10-01
申请号：US12410157
申请日：2009-03-24
申请人： Kazufumi KOMURA , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
发明人： Kazufumi KOMURA , Katsumi Furukawa , Keiichi Fujimura , Takayoshi Nakamura , Tohru Yasuda , Hirohisa Nishiyama , Nobuyoshi Nakaya , Kanta Yamamoto , Shigetaka Asano
IPC分类号： G01R31/02
CPC分类号： G01R31/318555 , G01R31/318533 , G01R31/318552
摘要： A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
摘要翻译：一种半导体器件包括：监测器，包括耦合在第一电源线和第二电源线之间的第一元件和用于增加第一元件与第一电源线或第二电源线之间的负载值的负载;以及确定单元，其基于所述监视器的输出来确定所述第一元素的操作状态。

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