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1. 发明授权

US07633147B2 Semiconductor unit having two device terminals for every one input/output signal 失效
标题翻译：半导体单元具有用于每一个输入/输出信号的两个器件端子
公开(公告)号：US07633147B2
公开(公告)日：2009-12-15
申请号：US10672551
申请日：2003-09-26
申请人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
发明人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
IPC分类号： H01L23/538
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.
摘要翻译：构成存储器件的半导体单元具有存储芯片，具有三个布线层的封装基板。电源表面（VDD表面）和（GND表面）被布线在封装衬底上，而封装内的DQ总线布线在两个电源表面之间的中间层上。存储器件每一个封装内DQ总线具有两个DQ引脚。封装内的DQ总线通过通孔连接到存储器芯片的信号端子焊盘。鉴于两个DW引脚，用于将封装内DQ DQ总线与信号端子焊盘连接的通孔构成分支线。

2. 发明授权

US06882241B2 Method, memory system and memory module board for avoiding local incoordination of impedance around memory chips on the memory system 有权
标题翻译：方法，存储器系统和存储器模块板，用于避免存储器系统上的存储器芯片周围的阻抗的局部不协调
公开(公告)号：US06882241B2
公开(公告)日：2005-04-19
申请号：US10255987
申请日：2002-09-26
申请人： Hisashi Abo , Hiroaki Ikeda
发明人： Hisashi Abo , Hiroaki Ikeda
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/00 , G11C5/06 , H01L27/10 , H05K1/02 , H05K1/14 , H03H7/38 , H03H5/00
CPC分类号： H05K1/14 , G11C5/063 , H01L2924/0002 , H05K1/0237 , H01L2924/00
摘要： A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.
摘要翻译：数据总线的信号线包括第一板上的第一布线和第二板上的第二布线。第二板安装在第一板上，以串联连接第一和第二导线以建立信号线。半导体器件与第二线连接。在这种数据总线系统中，根据第二板上的半导体器件的附加电容来确定第二布线的阻抗，以便使第一板的阻抗与第二板的阻抗相协调。

3. 发明授权

US6055209A Synchronous semiconductor memory device exhibiting an operation synchronous with an externally inputted clock signal 失效
标题翻译：具有与外部输入的时钟信号同步的操作的同步半导体存储器件
公开(公告)号：US6055209A
公开(公告)日：2000-04-25
申请号：US106101
申请日：1998-06-29
申请人： Hisashi Abo
发明人： Hisashi Abo
IPC分类号： G01R31/28 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/12 , G11C8/00
CPC分类号： G11C7/22
摘要： A synchronous semiconductor memory device has a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronizing with an externally inputted clock signal, an internal command signal having been generated in synchronizing with the externally inputted clock signal.
摘要翻译：同步半导体存储器件具有伪内部命令信号发生器，用于产生伪内部命令信号，该伪内部命令信号与外部输入的时钟信号不同步地控制与外部输入的时钟信号同步产生的内部命令信号。

4. 发明授权

US5822254A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5822254A
公开(公告)日：1998-10-13
申请号：US791034
申请日：1997-01-29
申请人： Yasuji Koshikawa , Hisashi Abo
发明人： Yasuji Koshikawa , Hisashi Abo
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/409 , H01L27/10
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069
摘要： A semiconductor memory device of a synchronous type is disclosed, which has an output control circuit (14) adapted to output signals D2T and D2N by activating one of two conduction control signals D1T or by inactivating both of the conduction control signals in accordance with an output control signal MSK2B or OEB for controlling whether a data output terminal DQ is to be actuated or set into a high impedance, and an output circuit 17 provided with a couple of latch circuits 15 and 16 each adapted to individually latch and output the corresponding conduction control signals in synchronism with an internal synchronizing signal .phi.3. There is further provided an additional latch circuit 13 latching the output control signal in response to an inverted signal of the internal synchronizing signal .phi.3.
摘要翻译：公开了一种同步型的半导体存储器件，其具有输出控制电路（14），该输出控制电路（14）适于通过激活两个导通控制信号D1T中的一个来输出信号D2T和D2N，或者通过根据输出来去激活两个导通控制信号控制信号MSK2B或OEB，用于控制数据输出端子DQ是被启动还是被设置为高阻抗;以及输出电路17，其设置有一对锁存电路15和16，每个锁存电路15和16分别适于锁存和输出相应的导通控制信号与内部同步信号phi3同步。还提供了一个附加锁存电路13，其响应于内部同步信号phi 3的反相信号来锁存输出控制信号。

5. 发明授权

US5872741A Semiconductor memory device having voltage converters 失效
标题翻译：具有电压转换器的半导体存储器件
公开(公告)号：US5872741A
公开(公告)日：1999-02-16
申请号：US969340
申请日：1997-11-28
申请人： Hisashi Abo
发明人： Hisashi Abo
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/22
摘要： A semiconductor memory device has a voltage converter for converting a voltage level of an internal clock signal to obtain a high voltage level clock signal. The high level clock signal accelerates the transmission of the clock signal to latch circuits which control the output transistors of the memory device. Another voltage converter is disposed between the data amplifier and the latch circuit instead of the output of the latch circuit, for prevention of current flowing through both the output transistors.
摘要翻译：半导体存储器件具有用于转换内部时钟信号的电压电平以获得高电压电平时钟信号的电压转换器。高电平时钟信号将时钟信号的传输加速到控制存储器件的输出晶体管的锁存电路。另一个电压转换器设置在数据放大器和锁存电路之间，而不是锁存电路的输出，以防止电流流过两个输出晶体管。

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