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1. 发明授权

US5822254A Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US5822254A
公开(公告)日：1998-10-13
申请号：US791034
申请日：1997-01-29
申请人： Yasuji Koshikawa , Hisashi Abo
发明人： Yasuji Koshikawa , Hisashi Abo
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/409 , H01L27/10
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069
摘要： A semiconductor memory device of a synchronous type is disclosed, which has an output control circuit (14) adapted to output signals D2T and D2N by activating one of two conduction control signals D1T or by inactivating both of the conduction control signals in accordance with an output control signal MSK2B or OEB for controlling whether a data output terminal DQ is to be actuated or set into a high impedance, and an output circuit 17 provided with a couple of latch circuits 15 and 16 each adapted to individually latch and output the corresponding conduction control signals in synchronism with an internal synchronizing signal .phi.3. There is further provided an additional latch circuit 13 latching the output control signal in response to an inverted signal of the internal synchronizing signal .phi.3.
摘要翻译：公开了一种同步型的半导体存储器件，其具有输出控制电路（14），该输出控制电路（14）适于通过激活两个导通控制信号D1T中的一个来输出信号D2T和D2N，或者通过根据输出来去激活两个导通控制信号控制信号MSK2B或OEB，用于控制数据输出端子DQ是被启动还是被设置为高阻抗;以及输出电路17，其设置有一对锁存电路15和16，每个锁存电路15和16分别适于锁存和输出相应的导通控制信号与内部同步信号phi3同步。还提供了一个附加锁存电路13，其响应于内部同步信号phi 3的反相信号来锁存输出控制信号。

2. 发明授权

US07742356B2 Semiconductor memory device having a refresh cycle changing circuit 有权
标题翻译：具有刷新周期改变电路的半导体存储器件
公开(公告)号：US07742356B2
公开(公告)日：2010-06-22
申请号：US11987767
申请日：2007-12-04
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.
摘要翻译：半导体存储器件包括：第一刷新周期改变电路，其根据自刷新模式改变刷新周期，而不影响根据自刷新模式的刷新周期;以及第二刷新周期改变电路，其改变刷新根据自刷新模式循环，而不会根据自动刷新模式对刷新周期产生影响。以这种方式，根据本发明，可以独立地控制根据自刷新模式的刷新周期和根据自刷新模式的刷新周期。因此，可以执行考虑每个模式的特性的刷新操作。

3. 发明申请

US20070242546A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070242546A1
公开(公告)日：2007-10-18
申请号：US11736421
申请日：2007-04-17
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40622 , G11C2211/4061
摘要： A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.
摘要翻译：半导体存储器件包括刷新计数器，用于当在正常操作中以预定间隔接收到刷新请求时，顺序产生指示要刷新的一个或多个字线对应的一个或多个行地址的计数值，其中刷新计数器分配给包括在行地址中的n位的n + 1级计数器和不包括在行地址中的伪位，并且从最低有效位到虚拟位的计数器部分形成N进制计数器，以便控制是否在接收刷新请求时响应于虚拟位的值来执行刷新。

4. 发明授权

US06175534B1 Synchronous semiconductor storage device 有权
标题翻译：同步半导体存储装置
公开(公告)号：US06175534B1
公开(公告)日：2001-01-16
申请号：US09299839
申请日：1999-04-26
申请人： Junya Taniguchi , Yasuji Koshikawa , Kouji Mine
发明人： Junya Taniguchi , Yasuji Koshikawa , Kouji Mine
IPC分类号： G11C800
CPC分类号： G01R31/31701
摘要： According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).
摘要翻译：根据一个公开的实施例，同步半导体存储装置（100）包括用于在进入测试模式之后完成模式设置操作的电路，其中测试模式包括较高频率的内部时钟。同步半导体存储装置（100）产生可以用于将模式设定值输入到模式寄存器设定电路（122）的第一内部同步时钟信号ICLK。同时，可以施加外部同步信号CSB以产生第二内部同步时钟信号CSCLK。 ICLK和CSCLK值可用于在测试模式下生成更高频率的时钟ICLK'。 ICLK信号可以应用于内部电路（124），允许这种电路以更高的速度运行。 ICLK信号不被施加到模式寄存器设置电路（122），从而避免模式寄存器设置电路（122）可能锁定不正确的模式设置值。

5. 发明授权

US6128247A Semiconductor memory device for making column decoder operable according to RAS access time 有权
标题翻译：用于使列解码器可根据RAS访问时间操作的半导体存储器件
公开(公告)号：US6128247A
公开(公告)日：2000-10-03
申请号：US474209
申请日：1999-12-29
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C11/407 , G11C8/10 , G11C8/18 , G11C11/401 , G11C8/00
CPC分类号： G11C8/18 , G11C8/10
摘要： A semiconductor memory device is disclosed, in which the output timing of an operation enabling signal for activating the column decoder can be suitably determined according to the RAS access time. The semiconductor memory device comprises a memory cell array; a row decoder for decoding row address data for designating a word line; a column decoder for decoding column address data for designating a data line; and a column decoder control section for outputting an operation enabling signal for making the column decoder operable to the column decoder. The column decoder control section determines the output timing of the operation enabling signal according to a determination of whether a sufficient RAS access time is obtained.
摘要翻译：公开了一种半导体存储器件，其中可以根据RAS访问时间来适当地确定用于激活列解码器的操作使能信号的输出定时。半导体存储器件包括存储单元阵列; 行解码器，用于解码用于指定字线的行地址数据; 列解码器，用于解码用于指定数据线的列地址数据; 以及列解码器控制部分，用于输出用于使列解码器可操作到列解码器的操作使能信号。列解码器控制部根据是否获得了足够的RAS访问时间的判定来决定操作使能信号的输出定时。

6. 发明授权

US6023433A Semiconductor memory device with a redundant decoder having a small scale in circuitry 有权
标题翻译：具有电路小规模的冗余解码器的半导体存储器件
公开(公告)号：US6023433A
公开(公告)日：2000-02-08
申请号：US182514
申请日：1998-10-30
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G01R31/28 , G11C29/00 , G11C29/02 , G11C29/04
CPC分类号： G11C29/80 , G11C29/02 , G11C29/808
摘要： In a semiconductor memory device comprising a regular memory cell array, a regular decoder, a redundant memory cell array, and a redundant decoder, the redundant decoder comprises a plurality of redundant decoding circuits each of which is supplied with a test mode signal. The redundant decoding circuits are supplied with an address signal and a complementary address signal in different order so that at least one pair of a bit in the address signal and a corresponding bit in the complementary address signal is supplied in the reverse sequence. The redundant decoder further comprises a decode inhibit signal producing arrangement for producing a decode inhibit signal indicative of active when any one of the redundant decoding circuits produces a redundant decoded signal indicative of active. Responsive to the decode inhibit signal indicative of inactive, the regular decoder decodes the address signal and the complementary address signal into a regular decoded signal for activating one of regular memory cells in the regular memory cell array. Each redundant decoding circuit comprises a test fuse circuit including a test fuse-element. The test fuse circuit produces a test fuse output signal indicative of active when the test fuse-element is not fused.
摘要翻译：在包括常规存储单元阵列，常规解码器，冗余存储单元阵列和冗余解码器的半导体存储器件中，冗余解码器包括多个冗余解码电路，每个冗余解码电路被提供有测试模式信号。冗余解码电路以不同的顺序提供地址信号和互补地址信号，使得地址信号中的至少一对位和互补地址信号中的对应位以相反顺序提供。冗余解码器还包括解码禁止信号产生装置，用于当任何一个冗余解码电路产生指示有效的冗余解码信号时产生指示有效的解码禁止信号。响应于指示不活动的解码禁止信号，常规解码器将地址信号和互补地址信号解码为用于激活常规存储器单元阵列中的常规存储器单元之一的常规解码信号。每个冗余解码电路包括包括测试熔丝元件的测试熔丝电路。测试熔丝电路产生一个测试保险丝输出信号，当测试熔丝元件未熔断时，该信号表示有效。

7. 发明授权

US5708614A Data output control circuit of semiconductor memory device having pipeline structure 失效
标题翻译：具有流水线结构的半导体存储器件的数据输出控制电路
公开(公告)号：US5708614A
公开(公告)日：1998-01-13
申请号：US784783
申请日：1997-01-16
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C29/00 , G01R31/28 , G11C11/413 , G11C29/14 , G11C29/34 , G11C29/38 , G11C29/50
CPC分类号： G11C29/14 , G11C29/38 , G11C29/50 , G06F2201/88
摘要： In a method of testing a semiconductor memory device having a pipeline structure, a same data is stored in a plurality of memory cells in advance. The stored data are read out from the plurality of memory cells to produce data signals and amplified as the data signals. A determining section determines whether all the data signals are same, to generate a determination result signal. In accordance with the determination result signal, one of signals associated with the amplified data signals and predetermined signals are transferred to an output section in synchronous with a synchronous signal. The output section includes a plurality of output circuits each of which provides, as an indication signal, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to each of the transferred signals. Therefore, using at least one of the indication signals, whether the plurality of memory cells are correctly operable can be tested.
摘要翻译：在测试具有流水线结构的半导体存储器件的方法中，预先将相同的数据存储在多个存储单元中。存储的数据从多个存储单元中读出以产生数据信号并作为数据信号进行放大。确定部分确定所有数据信号是否相同，以产生确定结果信号。根据确定结果信号，与放大数据信号和预定信号相关联的信号之一与同步信号同步地传送到输出部分。输出部分包括多个输出电路，每个输出电路响应于每个传送的信号，提供低电平信号，高电平信号和表示高阻抗状态的信号作为指示信号中的一个。因此，可以测试多个存储器单元是否正确可操作的至少一个指示信号。

8. 发明授权

US5539693A Method of controlling semiconductor storage circuit 失效
标题翻译：半导体存储电路的控制方法
公开(公告)号：US5539693A
公开(公告)日：1996-07-23
申请号：US362157
申请日：1994-12-22
申请人： Yasuji Koshikawa , Yasuhiro Takai
发明人： Yasuji Koshikawa , Yasuhiro Takai
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/413 , G11C11/40
CPC分类号： G11C7/1072 , G11C2207/2218
摘要： In the semiconductor integrated circuit of the present invention, write and read operation are successively implemented in which a manner that read addresses are inputted after write addresses are inputted and read data is read from a sense amplifier starting from the next cycle after all the data have been written to the sense amplifier.
摘要翻译：在本发明的半导体集成电路中，依次执行写入和读取操作，其中在写入地址之后输入读取地址的方式被输入，并且从所有数据具有的下一个周期开始从读出放大器读出读取数据被写入感测放大器。

9. 发明授权

US5502684A Semiconductor memory having high speed and low power data read/write circuit 失效
标题翻译：具有高速和低功率数据读/写电路的半导体存储器
公开(公告)号：US5502684A
公开(公告)日：1996-03-26
申请号：US351650
申请日：1994-12-07
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C11/41 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/1048
摘要： A semiconductor memory, particularly a sychronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level to a predetermined level after the write operation has completed.
摘要翻译：一种半导体存储器，特别是包括在写入操作中将读/写总线驱动到第一和第二电位的总线驱动电路的同步DRAM，在读取操作中将读/写总线驱动为第三和第四电位的数据放大器，以及预充电控制电路在写入操作完成之后将数据读/写总线预充电到预充电电平到预定电平。

10. 发明授权

US5397984A Integrated circuit for protecting internal circuitry from high voltage input test signals 失效
标题翻译：用于保护内部电路免受高压输入测试信号的集成电路
公开(公告)号：US5397984A
公开(公告)日：1995-03-14
申请号：US10166
申请日：1993-01-28
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A semiconductor integrated circuit protected against a high voltage testing signal is provided. The integrated circuit includes a first-stage input circuit, a discriminating circuit, a power suppuly circuit and a connecting circuit. The input ends of the-input circuit and the discriminating circuit are connected to one preselected external terminal. The discriminating circuit renders a testing circuit drive signal active to activate when a testing instruction signal higher than an ordinary input signal voltage is applied to the external terminal. When the testing circuit drive signal is active, the power supply circuit disconnects at least one of the positive and negative poles of the power source having polarity opposite to that of the testing instruction signal from the input circuit, and the connecting circuit connects one of the positive and negative poles of the power source having the same polarity as that of the testing instruction signal to the output end of the input circuit.
摘要翻译：提供了防止高电压测试信号的半导体集成电路。集成电路包括第一级输入电路，鉴别电路，电源电路和连接电路。输入电路和识别电路的输入端连接到一个预选的外部端子。当将高于普通输入信号电压的测试指令信号施加到外部端子时，识别电路使测试电路驱动信号有效以激活。当测试电路驱动信号有效时，电源电路断开与输入电路具有与测试指令信号相反的极性的电源的正极和负极中的至少一个，并且连接电路将电源的正极和负极具有与测试指令信号相同的极性到输入电路的输出端。

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