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1. 发明申请

US20050064699A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050064699A1
公开(公告)日：2005-03-24
申请号：US10940820
申请日：2004-09-15
申请人： Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
发明人： Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
IPC分类号： H01L27/00 , H01L21/28 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02164 , H01L21/02167 , H01L21/022 , H01L21/02271 , H01L21/02282 , H01L21/02337 , H01L21/3124 , H01L21/3148 , H01L21/31633 , H01L21/318 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835
摘要： A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.
摘要翻译：第一CVD绝缘层沉积在半导体衬底的表面上。接下来，在至少两个不同的步骤中沉积低k层，以在第一CVD电介质层上形成通孔层电介质膜和布线层电介质膜之一。沉积后立即进行热处理。在低k层上沉积第二CVD介电层。在第二CVD介质层和低k层中形成凹槽。在该结构上沉积金属层，填充凹槽。金属层通过化学机械抛光从第二CVD介电层去除。

2. 发明授权

US07125794B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07125794B2
公开(公告)日：2006-10-24
申请号：US10940820
申请日：2004-09-15
申请人： Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
发明人： Seiichi Kondo , Kaori Misawa , Shunichi Tokitoh , Takashi Nasuno
IPC分类号： H01L21/4763 , H01L21/312 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02164 , H01L21/02167 , H01L21/022 , H01L21/02271 , H01L21/02282 , H01L21/02337 , H01L21/3124 , H01L21/3148 , H01L21/31633 , H01L21/318 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835
摘要： A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.
摘要翻译：第一CVD绝缘层沉积在半导体衬底的表面上。接下来，在至少两个不同的步骤中沉积低k层，以在第一CVD电介质层上形成通孔层电介质膜和布线层电介质膜之一。沉积后立即进行热处理。在低k层上沉积第二CVD介电层。在第二CVD介质层和低k层中形成凹槽。在该结构上沉积金属层，填充凹槽。金属层通过化学机械抛光从第二CVD介电层去除。

3. 发明申请

US20050170641A1 Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device 审中-公开
标题翻译：多层布线结构，掩埋布线的形成方法，半导体器件，半导体器件的制造方法，半导体安装器件以及制造半导体安装器件的方法
公开(公告)号：US20050170641A1
公开(公告)日：2005-08-04
申请号：US11014883
申请日：2004-12-20
申请人： Seiichi Kondo , Kaori Misawa
发明人： Seiichi Kondo , Kaori Misawa
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L21/7684 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a buried wiring in a low-k dielectric film, includes: forming a low-k dielectric film having a dielectric constant of 3 or less on an underlayer; removing the low-k dielectric film by a first width from an edge of the underlayer; forming a cap film on the low-k dielectric film, after removing the low-k dielectric film by the first width; forming a groove in the cap film and the low-k dielectric film; forming a conductive film in the groove and on the cap film; removing the conductive film by a second width, different from the first width by 1 mm or more, from the edge of the underlayer; and polishing unnecessary portions of the conductive film on the cap film, after removing the conductive film by the second width.
摘要翻译：在低k电介质膜中形成掩埋布线的方法包括：在底层上形成介电常数为3以下的低k电介质膜; 从底层的边缘去除第一宽度的低k电介质膜; 在将低k电介质膜除去第一宽度之后，在低k电介质膜上形成盖膜; 在盖膜和低k电介质膜中形成凹槽; 在槽和盖膜中形成导电膜; 从所述底层的边缘除去所述导电膜的距离不同于所述第一宽度1mm以上的第二宽度; 并且在将导电膜除去第二宽度之后，在盖膜上抛光导电膜的不需要的部分。

4. 发明授权

US07064060B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07064060B2
公开(公告)日：2006-06-20
申请号：US11010344
申请日：2004-12-14
申请人： Kaori Misawa , Naofumi Ohashi
发明人： Kaori Misawa , Naofumi Ohashi
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/02107 , H01L21/02203 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31116 , H01L21/31138 , H01L21/31695 , H01L21/7682 , H01L21/76841 , H01L2221/1047
摘要： A heat treatment is performed to an insulating film composition, formed on a semiconductor substrate, at a temperature of 350° C. in an inert gas ambient to form a non-porous insulating film. Next, dry etching is performed using a resist pattern as a mask to form a trench in the non-porous insulating film, ashing is performed to remove the resist pattern, and the surface of the semiconductor substrate is cleaned. Thereafter, a second heat treatment is performed for the non-porous insulating film to form a porous insulating film. Since the second heat treatment is performed in an oxidizing-gas atmosphere, the pore-generating material can be removed at a temperature lower than the temperature of conventional methods to form an insulating film having a low dielectric constant.
摘要翻译：对形成在半导体基板上的绝缘膜组合物在惰性气体环境中在350℃的温度下进行热处理，以形成无孔绝缘膜。接下来，使用抗蚀剂图案作为掩模进行干蚀刻，以在无孔绝缘膜中形成沟槽，进行灰化以除去抗蚀剂图案，并且清洁半导体衬底的表面。此后，对无孔绝缘膜进行第二次热处理以形成多孔绝缘膜。由于在氧化气体气氛中进行第二热处理，所以可以在低于常规方法的温度的温度下除去孔产生材料，以形成具有低介电常数的绝缘膜。

5. 发明授权

US06177343B1 Process for producing semiconductor devices including an insulating layer with an impurity 有权
标题翻译：用于制造包括具有杂质的绝缘层的半导体器件的工艺
公开(公告)号：US06177343B1
公开(公告)日：2001-01-23
申请号：US09429698
申请日：1999-10-28
申请人： Hiroyuki Watanabe , Hideki Mizuhara , Kaori Misawa , Masaki Hirase , Hiroyuki Aoe
发明人： Hiroyuki Watanabe , Hideki Mizuhara , Kaori Misawa , Masaki Hirase , Hiroyuki Aoe
IPC分类号： H01L214763
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/022 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02282 , H01L21/02321 , H01L21/02351 , H01L21/3115 , H01L21/31155 , H01L21/3121 , H01L21/316 , H01L21/31612 , H01L21/31625 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76877
摘要： A semiconductor device and a process for producing the same. The device has two conducting layers that are spaced from each other and an insulating film for electrically insulating these two conducting layers from each other. The insulating film contains contact holes with plugs being embedded therein so as to electrically connect these two conducting layers by the plugs. The process contains a step of forming the insulating film on the lower conducting layer. An impurity having a kinetic energy is introduced into the insulating film. Next, contact holes are formed in the insulating film, and then plugs are formed in the contact holes. An upper conducting layer is formed on the insulating film so as to be electrically connected to the plugs.
摘要翻译：半导体器件及其制造方法。该器件具有彼此间隔开的两个导电层和用于将这两个导电层彼此电绝缘的绝缘膜。绝缘膜包含嵌入其中的插塞的接触孔，以便通过插头将这两个导电层电连接。该方法包括在下导电层上形成绝缘膜的步骤。具有动能的杂质被引入到绝缘膜中。接下来，在绝缘膜中形成接触孔，然后在接触孔中形成插塞。在绝缘膜上形成上导电层以与插头电连接。

6. 发明申请

US20100194960A1 CHARGE INCREASER 审中-公开
标题翻译：充电增加
公开(公告)号：US20100194960A1
公开(公告)日：2010-08-05
申请号：US12697441
申请日：2010-02-01
申请人： Hayato Nakashima , Mamoru Arimoto , Ryu Shimizu , Kaori Misawa
发明人： Hayato Nakashima , Mamoru Arimoto , Ryu Shimizu , Kaori Misawa
IPC分类号： H04N5/335
CPC分类号： H04N5/33 , A61B5/14532 , G01J5/34 , G01J2005/0077 , G01N27/122 , G01N27/3271 , G01N33/66 , H01L27/14609 , H01L27/14623 , H01L27/14649
摘要： This charge increaser includes a charge supplying portion having a signal source formed by a measurement object other than visible light and supplying signal charges corresponding to the signal source and a charge increasing portion for increasing the amount of charges corresponding to the signal charges stored in the charge supplying portion by measuring the measurement object other than visible light.
摘要翻译：该充电增量器包括具有由可见光以外的测量对象形成的信号源并且提供对应于信号源的信号电荷的电荷提供部分和用于增加与存储在电荷中的信号电荷相对应的电荷量的电荷增加部分通过测量除了可见光之外的测量对象来提供部分。

7. 发明申请

US20090144354A1 IMAGING DEVICE 审中-公开
标题翻译：成像装置
公开(公告)号：US20090144354A1
公开(公告)日：2009-06-04
申请号：US12324225
申请日：2008-11-26
申请人： Kaori Misawa , Ryu Shimizu , Mamoru Arimoto , Hayato Nakashima
发明人： Kaori Misawa , Ryu Shimizu , Mamoru Arimoto , Hayato Nakashima
IPC分类号： G06G7/16
CPC分类号： H01L27/14609 , H01L27/14603 , H01L31/035281
摘要： An imaging device that improves properties for multiplying signal charges. The imaging device includes an accumulation section which accumulates signal charges. A transfer section transfers the signal charges accumulated in the accumulation section. A multiplier section increases the signal charges accumulated in the accumulation section. The transfer section includes a first insulating member arranged on a substrate and a first electrode arranged on the first insulating member. The multiplier section includes a second insulating member arranged on the substrate and a second electrode arranged on the second insulating member. The second insulating member has a thickness which is greater than that of the first insulating member.
摘要翻译：一种成像装置，可改善乘法信号电荷的特性。成像装置包括累积信号电荷的累积部。传送部分传送累积部分中积累的信号电荷。乘法器部分增加累积部分中积累的信号电荷。转印部分包括布置在基底上的第一绝缘构件和布置在第一绝缘构件上的第一电极。乘法器部分包括布置在基板上的第二绝缘构件和布置在第二绝缘构件上的第二电极。第二绝缘构件的厚度大于第一绝缘构件的厚度。

8. 发明申请

US20090134437A1 IMAGE SENSOR AND CMOS IMAGE SENSOR 审中-公开
标题翻译：图像传感器和CMOS图像传感器
公开(公告)号：US20090134437A1
公开(公告)日：2009-05-28
申请号：US12274918
申请日：2008-11-20
申请人： Hayato Nakashima , Ryu Shimizu , Mamoru Arimoto , Kaori Misawa
发明人： Hayato Nakashima , Ryu Shimizu , Mamoru Arimoto , Kaori Misawa
IPC分类号： H01L31/02 , H01L27/00 , H01L27/105
CPC分类号： H01L27/14643 , H01L27/14806
摘要： In an image sensor, a first electrode, a second electrode, a third electrode and a fourth electrode are formed between a photoelectric conversion portion and a voltage conversion portion and are provided so as not to overlap with at least a part of the photoelectric conversion portion in plan view.
摘要翻译：在图像传感器中，第一电极，第二电极，第三电极和第四电极形成在光电转换部分和电压转换部分之间，并且设置成不与光电转换部分的至少一部分重叠在平面图。

9. 发明授权

US06998325B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06998325B2
公开(公告)日：2006-02-14
申请号：US10980279
申请日：2004-11-04
申请人： Takashi Yunogami , Kaori Misawa
发明人： Takashi Yunogami , Kaori Misawa
IPC分类号： H01L21/76
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76828 , H01L2221/1047
摘要： An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.
摘要翻译：将包含绝缘膜前体和孔产生材料的绝缘膜组合物施加到半导体衬底的表面上，并且进行第一热处理以使绝缘膜前体聚合而不使气孔产生材料蒸发，形成无孔绝缘膜。接下来，在无孔绝缘膜上形成抗蚀剂图案，并使用抗蚀剂图案作为掩模进行干法蚀刻，以在无孔绝缘膜中形成沟槽。通过灰化除去抗蚀剂图案后，清洁半导体衬底的表面。接下来，进行第二热处理以从无孔绝缘膜去除发孔材料并形成多孔绝缘膜。此后，在阻挡金属膜上的沟槽中沉积铜层以形成铜布线。

10. 发明申请

US20090315086A1 IMAGE SENSOR AND CMOS IMAGE SENSOR 审中-公开
标题翻译：图像传感器和CMOS图像传感器
公开(公告)号：US20090315086A1
公开(公告)日：2009-12-24
申请号：US12486495
申请日：2009-06-17
申请人： Mamoru Arimoto , Kaori Misawa , Hayato Nakashima , Ryu Shimizu
发明人： Mamoru Arimoto , Kaori Misawa , Hayato Nakashima , Ryu Shimizu
IPC分类号： H01L31/112 , H01L31/101
CPC分类号： H01L27/14603 , H01L27/14609
摘要： An image sensor includes a first electrode for applying a voltage to a charge storage portion, a second electrode for applying a voltage to a charge increasing portion, a third electrode provided between the first electrode and the second electrode and an impurity region of a first conductive type for forming a path through which the signal charges are transferred, wherein an impurity concentration of a region of the impurity region corresponding to a portion located under the second electrode is higher than an impurity concentration of a region of the impurity region corresponding to a portion located under the third electrode.
摘要翻译：图像传感器包括用于向电荷存储部分施加电压的第一电极，用于向电荷增加部分施加电压的第二电极，设置在第一电极和第二电极之间的第三电极和第一导电的杂质区域用于形成传送信号电荷的路径的类型，其中对应于位于第二电极下方的部分的杂质区域的杂质浓度高于对应于部分的杂质区域的杂质浓度位于第三电极下。

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