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1. 发明授权

US07278876B2 Connector in which two housings holding a cable are firmly engaged with each other 有权
公开(公告)号：US07278876B2
公开(公告)日：2007-10-09
申请号：US11645467
申请日：2006-12-26
申请人： Seiichi Hara , Kiminobu Tabata , Takeshi Kai , Tsutomu Fukui , Masaru Shinmura , Tadashi Inazu , Shigeki Takahashi
发明人： Seiichi Hara , Kiminobu Tabata , Takeshi Kai , Tsutomu Fukui , Masaru Shinmura , Tadashi Inazu , Shigeki Takahashi
IPC分类号： H01R13/85
CPC分类号： H01R13/582
摘要： A connector includes two housings coupled with each other to hold a cable therebetween. One of the housings includes a cable receiving portion for receiving the cable, a restricting portion adjacent to the cable receiving portion, a first wall portion formed outside the restricting portion and defining a space between the first wall portion and the restricting portion, and a first engaging portion inwardly protruding from the first wall portion. Another of the housings includes a cable pressing portion for pressing the cable towards the cable receiving portion and the restricting portion, and a second wall portion formed adjacent to the cable pressing portion and inserted into the space. The second wall portion has a second engaging portion extending outward from the second wall portion. The first and the second engaging potions are engaged with each other to prevent the housings from separating from each other.

2. 发明申请

US20070167066A1 Connector in which two housings holding a cable are firmly engaged with each other 有权
标题翻译：连接器，其中保持电缆的两个壳体彼此牢固地接合
公开(公告)号：US20070167066A1
公开(公告)日：2007-07-19
申请号：US11645467
申请日：2006-12-26
申请人： Seiichi Hara , Kiminobu Tabata , Takeshi Kai , Tsutomu Fukui , Masaru Shinmura , Tadashi Inazu , Shigeki Takahashi
发明人： Seiichi Hara , Kiminobu Tabata , Takeshi Kai , Tsutomu Fukui , Masaru Shinmura , Tadashi Inazu , Shigeki Takahashi
IPC分类号： H01R13/58
CPC分类号： H01R13/582
摘要： A connector includes two housings coupled with each other to hold a cable therebetween. One of the housings includes a cable receiving portion for receiving the cable, a restricting portion adjacent to the cable receiving portion, a first wall portion formed outside the restricting portion and defining a space between the first wall portion and the restricting portion, and a first engaging portion inwardly protruding from the first wall portion. Another of the housings includes a cable pressing portion for pressing the cable towards the cable receiving portion and the restricting portion, and a second wall portion formed adjacent to the cable pressing portion and inserted into the space. The second wall portion has a second engaging portion extending outward from the second wall portion. The first and the second engaging potions are engaged with each other to prevent the housings from separating from each other.
摘要翻译：连接器包括彼此联接以在其间保持电缆的两个壳体。其中一个壳体包括用于接收电缆的电缆接收部分，与电缆接收部分相邻的限制部分，形成在限制部分外部并限定第一壁部分和限制部分之间的空间的第一壁部分，以及第一接合部从第一壁部向内突出。另一个壳体包括用于将电缆朝向电缆接收部分和限制部分按压的电缆按压部分，以及邻近电缆按压部分形成并插入到该空间中的第二壁部分。第二壁部具有从第二壁部向外延伸的第二接合部。第一和第二接合部分彼此接合以防止壳体彼此分离。

3. 发明授权

US09274280B2 Optical waveguide type optical terminator 有权
标题翻译：光波导型光终端器
公开(公告)号：US09274280B2
公开(公告)日：2016-03-01
申请号：US14119746
申请日：2012-05-10
申请人： Jun Ushida , Shigeru Nakamura , Shigeki Takahashi
发明人： Jun Ushida , Shigeru Nakamura , Shigeki Takahashi
IPC分类号： G02B6/10 , G02B6/24 , G02B6/12
CPC分类号： G02B6/243 , G02B6/12 , G02B2006/12126
摘要： An optical waveguide type optical terminator forms an optical waveguide structure including at least an optical absorption core (103) which is formed on a clad layer (102) and includes a portion composed of silicon in which an impurity of 1019 cm−3 or more is doped, and is used by being optically connected in series with an optical waveguide including a core (105) composed of silicon. The optical absorption core (103) is sufficient provided that, at least, an impurity of around 1019 cm−3 is doped therein. For example, its impurity concentration is sufficient provided that it falls within a range of 1019-1020 cm−3. The existence of this impurity causes absorption of light in the optical absorption core (103).
摘要翻译：光波导型光学终端器形成至少包括形成在包层（102）上的光吸收芯（103）的光波导结构，其包括由1019cm-3以上的杂质为硅的硅构成的部分并且通过与包括由硅构成的芯（105）的光波导光学连接而被使用。光吸收芯（103）足够，只要至少掺杂约1019cm-3的杂质即可。例如，其杂质浓度足以在1019-1020cm-3的范围内。这种杂质的存在导致光吸收芯（103）中的光的吸收。

4. 发明授权

US09201196B2 High-order mode filter 有权
标题翻译：高阶模式滤波器
公开(公告)号：US09201196B2
公开(公告)日：2015-12-01
申请号：US14360107
申请日：2012-11-29
申请人： Shigeki Takahashi
发明人： Shigeki Takahashi
IPC分类号： G02B6/10 , G02B6/122 , G02B6/14 , G02B6/26 , G02B6/12
CPC分类号： G02B6/122 , G02B6/14 , G02B6/268 , G02B2006/12097 , G02B2006/12109
摘要： A high-order mode filter includes a slab region, a band-shaped projection elongated in an optical waveguide direction, a first optical waveguide including a disturbance element and a second optical waveguide. The disturbance element is formed by doping impurities into the slab region, thus indicating a lower refractive index than the slab region. Both the first optical waveguide and the second optical waveguide are alternately arranged. The first optical waveguide may include a disturbance element positioned close to the projection, while the second optical waveguide may include a disturbance element distanced from the projection in the slab region. The high-order mode filter causes a large high-order mode loss due to interference between a removable high-order mode and an intentional high-order mode at the connecting face between the first optical waveguide and the second optical waveguide, thus reducing reflected light and stray light.
摘要翻译：高阶模式滤波器包括平板区域，在光波导方向上延伸的带状突起，包括扰动元件的第一光波导和第二光波导。扰乱元件是通过将杂质掺杂到板坯区域中形成的，因此表示比板坯区域更低的折射率。第一光波导和第二光波导都交替布置。第一光波导可以包括靠近突起定位的扰动元件，而第二光波导可以包括远离板坯区域中的突起的扰动元件。高阶模式滤波器由于第一光波导和第二光波导之间的连接面处的可移除高阶模式和有意高阶模式之间的干涉而导致大的高阶模损耗，从而减少了反射光和杂散光。

5. 发明授权

US08488375B2 Magnetic recording element and nonvolatile memory device 有权
标题翻译：磁记录元件和非易失性存储器件
公开(公告)号：US08488375B2
公开(公告)日：2013-07-16
申请号：US13037592
申请日：2011-03-01
申请人： Daisuke Saida , Minoru Amano , Junichi Ito , Yuichi Ohsawa , Saori Kashiwada , Chikayoshi Kamata , Shigeki Takahashi
发明人： Daisuke Saida , Minoru Amano , Junichi Ito , Yuichi Ohsawa , Saori Kashiwada , Chikayoshi Kamata , Shigeki Takahashi
IPC分类号： G11C11/14
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , H01L27/228
摘要： According to one embodiment, a magnetic recording element includes a stacked body including a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer and a first nonmagnetic layer. Magnetization of the first ferromagnetic layer is substantially fixed in a first direction being perpendicular to a first ferromagnetic layer surface. The second stacked unit includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second nonmagnetic layer. Magnetization of the fourth ferromagnetic layer is substantially fixed in a second direction being perpendicular to a fourth ferromagnetic layer surface. The first direction is opposite to the second direction.
摘要翻译：根据一个实施例，磁记录元件包括包括第一堆叠单元和第二堆叠单元的堆叠体。第一堆叠单元包括第一铁磁层，第二铁磁层和第一非磁性层。第一铁磁层的磁化在垂直于第一铁磁层表面的第一方向上基本固定。第二堆叠单元包括第三铁磁层，第四铁磁层和第二非磁性层。第四铁磁层的磁化在垂直于第四铁磁层表面的第二方向上基本固定。第一方向与第二方向相反。

6. 发明申请

US20120244639A1 METHOD OF MANUFACTURING MAGNETIC MEMORY 失效
标题翻译：制造磁记忆的方法
公开(公告)号：US20120244639A1
公开(公告)日：2012-09-27
申请号：US13226868
申请日：2011-09-07
申请人： Yuichi OHSAWA , Shigeki Takahashi , Junichi Ito , Daisuke Saida , Kyoichi Suguro , Hiroaki Yoda
发明人： Yuichi OHSAWA , Shigeki Takahashi , Junichi Ito , Daisuke Saida , Kyoichi Suguro , Hiroaki Yoda
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , H01L29/82
摘要： According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning.
摘要翻译：根据一个实施例，一种制造磁存储器的方法，该方法包括形成具有可变磁化强度的第一磁性层，在第一磁性层上形成隧道势垒层，在隧道势垒层上形成第二磁性层，具有不变磁化的磁性层，在第二磁性层上形成硬掩模层作为掩模，通过使用硬掩模层的掩模对第二磁性层进行构图，并使用硬掩模的掩模执行GCIB照射层，图案后。

7. 发明申请

US20120182051A1 DRIVING CIRCUIT FOR TRANSISTOR 有权
标题翻译：驱动电路用于晶体管
公开(公告)号：US20120182051A1
公开(公告)日：2012-07-19
申请号：US13433624
申请日：2012-03-29
申请人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H03K3/00
CPC分类号： H01L27/0629 , H01L27/0255 , H03K17/063 , H03K17/165 , H03K17/168 , H03K17/567 , H03K17/687 , H03K2217/0036
摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
摘要翻译：开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。通过切换晶体管的控制电压，第一电极和第二电极之间的连接能够在导通状态和非导通状态之间暂时切换。齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。第一电极是漏极或集电极。

8. 发明申请

US20120139079A1 DIODE 有权
标题翻译：二极管
公开(公告)号：US20120139079A1
公开(公告)日：2012-06-07
申请号：US13296832
申请日：2011-11-15
申请人： Norihito TOKURA , Satoshi Shiraki , Shigeki Takahashi , Shinya Sakurai , Takashi Suzuki
发明人： Norihito TOKURA , Satoshi Shiraki , Shigeki Takahashi , Shinya Sakurai , Takashi Suzuki
IPC分类号： H01L29/47
CPC分类号： H01L21/76283 , H01L27/0814 , H01L27/1203 , H01L29/0619 , H01L29/0649 , H01L29/08 , H01L29/405 , H01L29/8611
摘要： A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.
摘要翻译：二极管在半导体层的表面上具有半导体层和阴极和阳极电极。半导体层具有分别与阴极和阳极电极接触的阴极和阳极区域。阳极区域具有表面浓度高的第一扩散区域，具有中间表面浓度的第二扩散区域和具有低表面浓度的第三扩散区域。第一扩散区被第二和第三扩散区覆盖。第二扩散区域具有面对阴极区域的第一侧表面，与阴极区域相对的第二侧表面和在第一和第二侧表面之间延伸的底表面。第三扩散区域覆盖连接第一侧表面与底表面的第一角部和将第二侧表面与底表面连接的第二角部中的至少一个。

9. 发明申请

US20110210766A1 DRIVING CIRCUIT FOR TRANSISTOR 有权
标题翻译：驱动电路用于晶体管
公开(公告)号：US20110210766A1
公开(公告)日：2011-09-01
申请号：US13105021
申请日：2011-05-11
申请人： Takaaki AOKI , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Takaaki AOKI , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H03B1/00
CPC分类号： H01L27/0629 , H01L27/0255 , H03K17/063 , H03K17/165 , H03K17/168 , H03K17/567 , H03K17/687 , H03K2217/0036
摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
摘要翻译：开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。通过切换晶体管的控制电压，第一电极和第二电极之间的连接能够在导通状态和非导通状态之间暂时切换。齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。第一电极是漏极或集电极。

10. 发明申请

US20110073904A1 Semiconductor device having SOI substrate and method for manufacturing the same 有权
标题翻译：具有SOI衬底的半导体器件及其制造方法
公开(公告)号：US20110073904A1
公开(公告)日：2011-03-31
申请号：US12923469
申请日：2010-09-23
申请人： Youichi Ashida , Norihito Tokura , Shigeki Takahashi , Yoshiaki Nakayama , Satoshi Shiraki , Kouji Senda
发明人： Youichi Ashida , Norihito Tokura , Shigeki Takahashi , Yoshiaki Nakayama , Satoshi Shiraki , Kouji Senda
IPC分类号： H01L29/739 , H01L29/06 , H01L29/78 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/84 , H01L29/0634 , H01L29/0657 , H01L29/0692 , H01L29/1608 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66128 , H01L29/7394 , H01L29/7824 , H01L29/8611
摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.
摘要翻译：半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。交替地布置第一和第二导电类型区域。第一和第二导电类型区域具有对应于半导体元件的布局。

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