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1. 发明申请

US20070111469A1 Method for fabricating semiconductor device with bulb-shaped recess gate 审中-公开
标题翻译：制造具有灯泡形凹槽的半导体器件的方法
公开(公告)号：US20070111469A1
公开(公告)日：2007-05-17
申请号：US11477536
申请日：2006-06-30
申请人： Sei-Jin Kim , Ki-Won Nam
发明人： Sei-Jin Kim , Ki-Won Nam
IPC分类号： H01L21/76
CPC分类号： H01L21/823437 , H01L21/28114 , H01L29/4236 , H01L29/42376 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes: forming a pad oxide layer over a substrate; forming a hard mask pattern over the pad oxide layer; etching a predetermined portion of the pad oxide layer and the substrate using the hard mask pattern to form a first recess having sidewalls and a bottom portion; forming a spacer over the hard mask pattern and on the sidewalls and the bottom portion of the first recess; and etching the substrate beneath the first recess using the spacer as an etch barrier to form a second recess, the second recess being wider and more rounded than the first recess.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成衬垫氧化层; 在所述焊盘氧化物层上形成硬掩模图案; 使用所述硬掩模图案蚀刻所述焊盘氧化物层和所述衬底的预定部分以形成具有侧壁和底部的第一凹部; 在所述硬掩模图案上方和所述第一凹部的所述侧壁和所述底部上形成间隔物; 以及使用所述间隔件作为蚀刻阻挡层来蚀刻所述第一凹部下方的所述基底以形成第二凹部，所述第二凹部比所述第一凹部更宽且更圆。

2. 发明申请

US20060292884A1 Method for fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060292884A1
公开(公告)日：2006-12-28
申请号：US11473489
申请日：2006-06-22
申请人： Ki-Won Nam , Sei-Jin Kim
发明人： Ki-Won Nam , Sei-Jin Kim
IPC分类号： H01L21/302 , H01L21/311
CPC分类号： H01L21/32137 , H01L27/10891
摘要： A method for fabricating a semiconductor device includes forming a polysilicon layer, a silicide layer and a hard mask over a semiconductor substrate, etching the silicide layer using the hard mask as an etch barrier, shaping the silicide layer with a predetermined profile using a mixed gas, and etching the polysilicon layer using the hard mask as an etch barrier.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成多晶硅层，硅化物层和硬掩模，使用硬掩模作为蚀刻阻挡层蚀刻硅化物层，使用混合气体以预定的形状对硅化物层进行成形，并使用硬掩模作为蚀刻阻挡层蚀刻多晶硅层。

3. 发明授权

US07269085B2 Non volatile semiconductor memory device having a multi-bit cell array 有权
标题翻译：具有多位单元阵列的非易失性半导体存储器件
公开(公告)号：US07269085B2
公开(公告)日：2007-09-11
申请号：US11317429
申请日：2005-12-23
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.
摘要翻译：提供半导体器件。半导体器件包括：存储非易失性状态的弱电池的地址的存储部; 以及动态半导体存储器件，包括：具有正常单元的存储单元阵列和要刷新的弱单元; 以及对所述弱小区执行刷新操作的刷新控制部分，其中当刷新操作模式中应用的地址与存储在存储部分中的地址一致时，所述弱小区的刷新周期短于正常小区的刷新周期。

4. 发明授权

US08055854B2 System having memory device accessible to multiple processors 有权
标题翻译：具有可访问多个处理器的存储器件的系统
公开(公告)号：US08055854B2
公开(公告)日：2011-11-08
申请号：US11342848
申请日：2006-01-31
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F12/1072 , G06F12/109 , Y02D10/13
摘要： A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.
摘要翻译：提供了具有可由多个处理器访问的存储器件的系统。该系统包括存储器件，第一处理器和第二处理器。存储器件具有第一存储器阵列部分和第二存储器阵列部分。第一处理器主要访问存储器件的第一存储器阵列部分并且选择性地访问存储器件的第二存储器阵列部分。第二处理器主要访问存储器件的第二存储器阵列部分并且选择性地访问存储器件的第一存储器阵列部分。

5. 发明申请

US20060236041A1 System having memory device accessible to multiple processors 有权
标题翻译：具有可访问多个处理器的存储器件的系统
公开(公告)号：US20060236041A1
公开(公告)日：2006-10-19
申请号：US11342848
申请日：2006-01-31
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G06F12/14
CPC分类号： G06F12/04 , G06F12/1072 , G06F12/109 , Y02D10/13
摘要： A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.
摘要翻译：提供了具有可由多个处理器访问的存储器件的系统。该系统包括存储器件，第一处理器和第二处理器。存储器件具有第一存储器阵列部分和第二存储器阵列部分。第一处理器主要访问存储器件的第一存储器阵列部分并且选择性地访问存储器件的第二存储器阵列部分。第二处理器主要访问存储器件的第二存储器阵列部分并且选择性地访问存储器件的第一存储器阵列部分。

6. 发明申请

US20060161338A1 Multi-port memory device providing protection signal 失效
公开(公告)号：US20060161338A1
公开(公告)日：2006-07-20
申请号：US11345054
申请日：2006-02-01
申请人： Han-Gu Sohn , Woon-Sik Suh , Yun-Tae Lee , Sei-Jin Kim
发明人： Han-Gu Sohn , Woon-Sik Suh , Yun-Tae Lee , Sei-Jin Kim
IPC分类号： G01C21/34
CPC分类号： G11C7/1075 , G06F13/1647 , G11C7/1012 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C11/4087 , G11C11/4096
摘要： A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.

7. 发明申请

US20050071582A1 Circuits and methods for providing variable data I/O width for semiconductor memory devices 有权
标题翻译：用于为半导体存储器件提供可变数据I / O宽度的电路和方法
公开(公告)号：US20050071582A1
公开(公告)日：2005-03-31
申请号：US10732868
申请日：2003-12-10
申请人： Han-Gu Sohn , Hai-Jeong Sohn , Sei-Jin Kim , Woo-seop Jeong
发明人： Han-Gu Sohn , Hai-Jeong Sohn , Sei-Jin Kim , Woo-seop Jeong
IPC分类号： G11C11/407 , G06F12/00 , G06F12/04 , G06F13/00 , G11C7/10
CPC分类号： G11C7/1057 , G06F12/04 , G11C7/10 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.
摘要翻译：用于控制半导体存储器件中数据I / O操作的电路和方法，为读，写和有效存储器操作提供可变数据I / O宽度。用于选择性地控制数据I / O缓冲器的数据宽度的电路和方法，以便在存储器访问操作期间实现可变数据I / O宽度。

8. 发明授权

US07539825B2 Multi-port memory device providing protection signal 失效
标题翻译：多端口存储器件提供保护信号
公开(公告)号：US07539825B2
公开(公告)日：2009-05-26
申请号：US11345054
申请日：2006-02-01
申请人： Han-Gu Sohn , Woon-Sik Suh , Yun-Tae Lee , Sei-Jin Kim
发明人： Han-Gu Sohn , Woon-Sik Suh , Yun-Tae Lee , Sei-Jin Kim
IPC分类号： G06F12/00 , G06F13/18
CPC分类号： G11C7/1075 , G06F13/1647 , G11C7/1012 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C11/4087 , G11C11/4096
摘要： A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.
摘要翻译：存储器系统包括连接到第一和第二外部设备的第一外部设备，第二外部设备和多端口存储设备。多端口存储器系统包括：分别连接到第一和第二外部设备的第一端口和第二端口，具有至少一个存储体的第一组组，第一组组被配置为由第一外部设备通过第一个数据端口; 具有至少一个存储体的第二组组，所述第二组组被配置为通过所述第二数据端口被所述第二外部设备访问; 具有至少一个存储体的第三组组，其中所述第三组组被配置为通过所述第一数据端口或所述第二外部设备通过所述第二数据端口被所述第一外部设备选择性地访问。多端口存储器系统可以防止当两个端口同时尝试访问同一存储体时发生的数据冲突。

9. 发明授权

US07099207B2 Semiconductor memory device and method for masking predetermined area of memory cell array during write operation 失效
标题翻译：半导体存储器件和用于在写入操作期间屏蔽存储器单元阵列的预定区域的方法
公开(公告)号：US07099207B2
公开(公告)日：2006-08-29
申请号：US11104072
申请日：2005-04-12
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C16/22
摘要： A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.
摘要翻译：半导体器件包括存储单元阵列，其包括存储从闪速存储器接收的程序数据的多个存储单元中的至少一个，响应于第一选通信号接收行地址信号的行地址缓冲器，以及列地址缓冲器，其响应于第二选通信号而接收列地址信号。该装置还包括响应于第一控制信号启用/禁用的写保护电路，写保护电路响应于行地址信号，第二选通信号和第二控制信号在使能时输出屏蔽控制信号，以及列解码器，其响应于掩蔽控制信号对列地址信号进行解码，并且使能与解码列地址信号相对应的存储单元阵列的多个列选择线中的至少一个，或禁用列选择线。

10. 发明申请

US20050248983A1 Semiconductor memory device and method for masking predetermined area of memory cell array during write operation 失效
标题翻译：半导体存储器件和用于在写入操作期间屏蔽存储器单元阵列的预定区域的方法
公开(公告)号：US20050248983A1
公开(公告)日：2005-11-10
申请号：US11104072
申请日：2005-04-12
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G11C16/02 , G11C11/34 , G11C16/22
CPC分类号： G11C16/22
摘要： A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.
摘要翻译：半导体器件包括存储单元阵列，其包括存储从闪速存储器接收的程序数据的多个存储单元中的至少一个，响应于第一选通信号接收行地址信号的行地址缓冲器，以及列地址缓冲器，其响应于第二选通信号而接收列地址信号。该装置还包括响应于第一控制信号启用/禁用的写保护电路，写保护电路响应于行地址信号，第二选通信号和第二控制信号在使能时输出屏蔽控制信号，以及列解码器，其响应于掩蔽控制信号对列地址信号进行解码，并且使能与解码列地址信号相对应的存储单元阵列的多个列选择线中的至少一个，或禁用列选择线。

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