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1. 发明授权

US06546379B1 Cascade boosting of predictive models 失效
标题翻译：级联提升预测模型
公开(公告)号：US06546379B1
公开(公告)日：2003-04-08
申请号：US09427064
申请日：1999-10-26
申请人： Se June Hong , Barry K. Rosen
发明人： Se June Hong , Barry K. Rosen
IPC分类号： G06F1518
CPC分类号： G06K9/6256 , G06N5/025 , G06N99/005
摘要： A method of boosting of predictive models, called cascade boosting, for resolving the interpretability problem of previous boosting methods while mitigating the fragmentation problem when applied to decision trees. This method of cascade boosting always applies a single weak model to any given data point. An improvement to the common method of boosting lies in how weak models are organized in a decision list rather than a weighted average. Cascade boosting resolves the interpretability problem of previous boosting methods while mitigating the fragmentation problem when applied to decision trees. Cascade boosting is simplest when applied to segmented predictive models but may also be applied to predictive models that do not explicitly segment the space of possible data points. The predictive model resulting from cascade boosting has fewer rules, or tree leaves, thereby enabling a modeler to better understand the correlations among the data.
摘要翻译：一种提高预测模型的方法，称为级联升压，用于解决先前的升压方法的可解释性问题，同时在应用于决策树时减轻分段问题。这种级联升压的方法总是将单个弱模型应用于任何给定的数据点。普遍提升方法的改进在于决策列表中组织的模型薄弱，而不是加权平均数。级联提升解决了以前的提升方法的可解释性问题，同时在应用于决策树时减轻了碎片问题。级联升压在应用于分段预测模型时最简单，但也可应用于未明确分割可能数据点空间的预测模型。由级联提升产生的预测模型具有较少的规则或树叶，从而使建模者能够更好地了解数据之间的相关性。

2. 发明授权

US4763289A Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits 失效
标题翻译：互补金属氧化物半导体电路的建模和故障模拟方法
公开(公告)号：US4763289A
公开(公告)日：1988-08-09
申请号：US815435
申请日：1985-12-31
申请人： Zeev Barzilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
发明人： Zeev Barzilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
IPC分类号： G01R31/302 , G01R31/3183 , G06F11/25 , G06F17/50 , G06F15/20 , G06F11/22
CPC分类号： G01R31/318357 , G01R31/3183 , G06F17/5022
摘要： A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.
摘要翻译：考虑由于电荷存储和静电危害引起的电路行为影响，通过布尔门对互补金属氧化物半导体（CMOS）组合逻辑电路进行建模的方法。模型是为每个电路的无故障和故障运行而开发的。根据本发明的另一方面，这些模型用于模拟过程中以评估使用多个这些电路构建的大规模集成电路设计的故障覆盖。在评估过程中，故障模型仅用于正在测试其故障性能的特定电路，并且所有其他电路都使用无故障模型。该过程继续进行，直到所有单独的门电路都被评估为止。

3. 发明授权

US4727313A Fault simulation for differential cascode voltage switches 失效
标题翻译：差分共源共栅电压开关的故障模拟
公开(公告)号：US4727313A
公开(公告)日：1988-02-23
申请号：US709612
申请日：1985-03-08
申请人： Zeev Barazilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
发明人： Zeev Barazilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
IPC分类号： G01R31/28 , G06F11/26 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261
摘要： A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.
摘要翻译：通过用三段布尔树替换每个开关级逻辑树，来模拟差分共源共栅电压开关电路（domino circuit）的方法。在每个部分中，开关由AND门代替。第一和第三部分在一个方向上传递信号，而第二部分在相反的方向上传递信号。这三个部分是端对端互连的。可以通过保持所选内部信号的故障值来模拟各种故障。

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