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1. 发明授权

US5246537A Method of forming recessed oxide isolation 失效
标题翻译：形成凹陷氧化物隔离的方法
公开(公告)号：US5246537A
公开(公告)日：1993-09-21
申请号：US876146
申请日：1992-04-30
申请人： Kent J. Cooper , Scott S. Roth , Wayne J. Ray , Howard C. Kirsch
发明人： Kent J. Cooper , Scott S. Roth , Wayne J. Ray , Howard C. Kirsch
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76227
摘要： A method requiring only a single mask results in an isolation oxide (50) which is the same size as, instead of becoming larger than, the dimension originally defined by the lithographic system. A buffer layer (14) is formed over the substrate (12). An oxidation resistant layer (16) is formed over the buffer layer (14). The oxidation resistant layer (16) is etched and a disposable sidewall spacer (30) is formed adjacent to the sidewall of the oxidation resistant layer (28), and a trench region is defined (36). The trench region (36) is etched to form a trench. The disposable sidewall spacer (30) is removed and a conformal layer (48) of oxidizable material is deposited over the trench sidewall (40) and the trench bottom surface (38). The conformal layer (48) is then oxidized to form electrical isolation in the isolation regions (26) of the substrate (12).
摘要翻译：仅需要单个掩模的方法产生与原始由光刻系统定义的尺寸相同的尺寸的隔离氧化物（50），而不是变大。在衬底（12）上形成缓冲层（14）。在缓冲层（14）上形成抗氧化层（16）。蚀刻抗氧化层（16），并且邻近抗氧化层（28）的侧壁形成一次侧壁间隔物（30），并且限定沟槽区域（36）。蚀刻沟槽区域（36）以形成沟槽。一次性侧壁间隔件（30）被去除，并且可氧化材料的共形层（48）沉积在沟槽侧壁（40）和沟槽底表面（38）上。然后将保形层（48）氧化以在衬底（12）的隔离区域（26）中形成电隔离。

2. 发明授权

US5272117A Method for planarizing a layer of material 失效
标题翻译：平面化材料层的方法
公开(公告)号：US5272117A
公开(公告)日：1993-12-21
申请号：US986303
申请日：1992-12-07
申请人： Scott S. Roth , Wayne J. Ray , Howard C. Kirsch
发明人： Scott S. Roth , Wayne J. Ray , Howard C. Kirsch
IPC分类号： H01L21/768 , H01L21/465
CPC分类号： H01L21/76819
摘要： A method for forming a planarized layer of material starts by providing a substrate (12). An integrated circuit layer (14) is formed overlying the substrate (12). A first layer of material (16) is formed overlying the integrated circuit layer (14). An etch stop layer (18) is formed overlying the layer of material (16) and etched to form sidewall formations or spacers. A second layer of material (20) is formed overlying the layer of material (16) and the etch stop layer (18). Planarization, polishing, or etch-back processing is performed using the etch stop layer (18) to endpoint. The resulting planarized layer has a thickness which is determined accurately by the etch stop layer (18).
摘要翻译：用于形成平坦化材料层的方法通过提供衬底（12）开始。在衬底（12）上形成集成电路层（14）。第一层材料（16）形成在该集成电路层（14）上。形成覆盖在材料层（16）上的蚀刻停止层（18），并被蚀刻以形成侧壁结构或间隔物。形成第二层材料（20），覆盖材料层（16）和蚀刻停止层（18）。使用蚀刻停止层（18）至端点进行平面化，抛光或回蚀刻处理。得到的平坦化层具有由蚀刻停止层（18）精确确定的厚度。

3. 发明授权

US5543339A Process for forming an electrically programmable read-only memory cell 失效
标题翻译：用于形成电可编程只读存储器单元的工艺
公开(公告)号：US5543339A
公开(公告)日：1996-08-06
申请号：US296908
申请日：1994-08-29
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/8247 , H01L29/423
CPC分类号： H01L27/11521 , H01L29/42324
摘要： A floating gate (51) is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
摘要翻译：浮动栅极（51）形成为具有增加浮动栅极（51）和存储单元的控制栅极之间的电容耦合的空腔（52）。存储单元可以用在EPROM，EEPROM和闪存EEPROM阵列中，并且可以通过热载流子注入，Fowler-Nordheim隧道等来编程和擦除。用于形成浮动栅极（51）的空腔（52）的工艺顺序具有良好的工艺裕度，允许一些光刻未对准。在一个实施例中，可以形成多层浮动栅极。多层结构允许电容耦合进一步增加而不占用更多的面积。

4. 发明授权

US5445107A Semiconductor device and method of formation 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US5445107A
公开(公告)日：1995-08-29
申请号：US155607
申请日：1993-11-22
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： C30B1/02
CPC分类号： H01L27/1203 , C30B1/023 , C30B29/06 , H01L21/84
摘要： A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) is subsequently annealed to form a monocrystalline layer of epitaxial silicon (38). Because the amorphous silicon layer (36) is in contact with only the silicon substrate (12), during the re-growth process, the resulting epitaxial layer (38) is formed with a reduced number of crystal defects. The resulting epitaxial silicon layer (38) may then be used to form semiconductor devices.
摘要翻译：通过固相外延再生长形成硅上绝缘膜（38）。形成一层非晶硅（36），使其仅与硅衬底（12）的下部直接接触。然后将非晶硅层（36）退火以形成外延硅单晶层（38）。由于非晶硅层（36）仅与硅衬底（12）接触，所以在再生长过程中，所形成的外延层（38）形成数量减少的晶体缺陷。然后可以使用所得的外延硅层（38）来形成半导体器件。

5. 发明授权

US5308997A Self-aligned thin film transistor 失效
标题翻译：自对准薄膜晶体管
公开(公告)号：US5308997A
公开(公告)日：1994-05-03
申请号：US902216
申请日：1992-06-22
申请人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
发明人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
IPC分类号： H01L29/78 , H01L21/336 , H01L27/11 , H01L29/417 , H01L29/786 , H01L29/04 , H01L27/01 , H01L31/036
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/41733 , H01L29/66757
摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
摘要翻译：在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔件（130）的第二部分 124）。邻近半导体侧壁间隔物（130）形成介电层（132）。与电介质层（132）相邻地形成控制电极（134）。

6. 发明授权

US5118639A Process for the formation of elevated source and drain structures in a semiconductor device 失效
标题翻译：在半导体器件中形成升高的源极和漏极结构的工艺
公开(公告)号：US5118639A
公开(公告)日：1992-06-02
申请号：US529299
申请日：1990-05-29
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/336 , H01L29/08
CPC分类号： H01L29/66575 , H01L29/0847 , H01L29/41783
摘要： A semiconductor device is disclosed having elevated source and drain regions formed by selectively depositing silicon onto a patterned layer of silicon which acts as a nucleation site for the propagation of the selective deposition process. In accordance with one embodiment of the invention, a silicon substrate is provided of a first conductivity type having an active surface area surrounded by an isolation region. A gate dielectric is formed overlying the active surface area of the substrate and a gate electrode is formed on a central portion of the active surface area. An insulation layer is formed which encapsulates the gate electrode and a first layer of silicon is deposited on the substrate. The first silicon layer is patterned to form a patterned portion overlying the active surface area and the isolation region which is spaced apart from the gate electrode by the insulation layer overlying the gate electrode. A second layer of electrically conductive material is selectively deposited using the patterned portion of the first silicon layer as a nucleation site and an impurity of a second conductivity type is introduced into the second layer of silicon. The selectively deposited layer of electrically conductive material forms elevated source and drain regions which make electrical contact with the active surface area and are electrically insulated from the gate electrode by the insulation layer encapsulating the gate electrode.
摘要翻译：公开了一种半导体器件，其具有通过选择性地将硅沉积到图案化硅层上形成的升高的源极和漏极区域，其作为用于选择性沉积工艺的传播的成核位置。根据本发明的一个实施例，提供具有由隔离区域包围的有源表面区域的第一导电类型的硅衬底。在衬底的有源表面区域上形成栅极电介质，并且在有源表面区域的中心部分上形成栅电极。形成绝缘层，其封装栅电极，并且第一层硅沉积在衬底上。图案化第一硅层以形成覆盖有源表面区域的图案化部分和通过覆盖栅电极的绝缘层与栅电极间隔开的隔离区域。使用第一硅层的图案化部分作为成核位置选择性地沉积第二层导电材料，并且将第二导电类型的杂质引入到第二硅层中。导电材料的选择性沉积层形成升高的源极和漏极区域，其与有源表面区域电接触并且通过封装栅电极的绝缘层与栅电极电绝缘。

7. 发明授权

US5616941A Electrically programmable read-only memory cell 失效
标题翻译：电可编程只读存储单元
公开(公告)号：US5616941A
公开(公告)日：1997-04-01
申请号：US531357
申请日：1995-09-20
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/8247 , H01L29/423 , H01C29/788 , H01C27/148
CPC分类号： H01L27/11521 , H01L29/42324
摘要： A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
摘要翻译：浮动栅极（51）形成为具有增加浮动栅极（51）和存储单元的控制栅极之间的电容耦合的空腔（52）。存储单元可以用在EPROM，EEPROM和闪存EEPROM阵列中，并且可以通过热载流子注入，Fowler-Nordheim隧道等来编程和擦除。用于形成浮动栅极（51）的空腔（52）的工艺顺序具有良好的工艺裕度，允许一些光刻未对准。在一个实施例中，可以形成多层浮动栅极。多层结构允许电容耦合进一步增加而不占用更多的面积。

8. 发明授权

US5374573A Method of forming a self-aligned thin film transistor 失效
标题翻译：形成自对准薄膜晶体管的方法
公开(公告)号：US5374573A
公开(公告)日：1994-12-20
申请号：US200591
申请日：1994-02-23
申请人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
发明人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
IPC分类号： H01L29/78 , H01L21/336 , H01L27/11 , H01L29/417 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/41733 , H01L29/66757
摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
摘要翻译：在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔物（130）的第二部分 124）。邻近半导体侧壁间隔物（130）形成介电层（132）。与电介质层（132）相邻地形成控制电极（134）。

9. 发明授权

US5286674A Method for forming a via structure and semiconductor device having the same 失效
标题翻译：用于形成通孔结构的方法和具有该通孔结构的半导体器件
公开(公告)号：US5286674A
公开(公告)日：1994-02-15
申请号：US844044
申请日：1992-03-02
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , Y10S438/97
摘要： A semiconductor device (20) makes contact between a first metal line (22) and an overlying second metal line (24) without the need for a conductive landing pad. Sidewall spacers (30) are formed adjacent sides of metal lines (22) such that during formation of a via (34) in an overlying dielectric layer (32), the sidewall spacer prevent trenching of underlying dielectric layer (28) if the via is misaligned. The sidewall spacers are formed of a dielectric material which has an etch rate which is significantly slower than the etch rate of dielectric layer (32). In another embodiment, portions of the sidewall spacers are selectively removed prior to depositing a second metal layer (42). Upon depositing the second metal layer, the side of metal line (22) is locally clad with the second metal to increase contact area and lowering contact resistance.
摘要翻译：半导体器件（20）在第一金属线（22）和上覆的第二金属线（24）之间接触，而不需要导电的着陆焊盘。在金属线（22）的相邻侧面处形成侧壁间隔件（30），使得在形成覆盖介质层（32）中的通路（34）时，侧壁间隔物防止下面的介电层（28）的沟槽，如果通孔是不对齐侧壁间隔物由电介质材料形成，该电介质材料具有比介电层（32）的蚀刻速率显着更慢的蚀刻速率。在另一个实施例中，在沉积第二金属层（42）之前选择性地去除侧壁间隔物的部分。在沉积第二金属层时，金属线（22）的一侧用第二金属局部包覆以增加接触面积并降低接触电阻。

10. 发明授权

US5538922A Method for forming contact to a semiconductor device 失效
标题翻译：形成与半导体器件的接触的方法
公开(公告)号：US5538922A
公开(公告)日：1996-07-23
申请号：US378990
申请日：1995-01-25
申请人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
发明人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
IPC分类号： H01L21/60 , H01L21/46
CPC分类号： H01L21/76897 , Y10S148/02 , Y10S438/97
摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.
摘要翻译：接触形成在半导体器件（10）中，与底层的形貌或间距无关。在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。在绝缘层上沉积蚀刻停止层（20）。在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

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