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1. 发明申请

US20130051497A1 Method and Apparatus for Implementing Slice-Level Adjustment 有权
标题翻译：实施切片调整的方法和装置
公开(公告)号：US20130051497A1
公开(公告)日：2013-02-28
申请号：US13219490
申请日：2011-08-26
申请人： Scott McLeod , Nikola Nedovic
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H04L27/06
CPC分类号： H04B10/695 , H04L7/0087 , H04L7/033
摘要： In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.
摘要翻译：在一个实施例中，接收机可以从发射机接收信号。接收机可以包括当信号的值为零时可以对信号进行采样的第一采样器。接收机还可以包括第二采样器，其可以在第一采样器对信号进行采样的时间与第一采样器对信号进行采样以产生一组采样值的下一次之间取样信号。如果采样值大于参考电压的值，则接收机可以进一步可操作以确定采样值集合中的采样值为逻辑1，并且如果采样值较小，采样值为逻辑0 比参考电压的值。

2. 发明申请

US20070215928A1 Fringe capacitor using bootstrapped non-metal layer 有权
标题翻译：边缘电容器采用自举非金属层
公开(公告)号：US20070215928A1
公开(公告)日：2007-09-20
申请号：US11384961
申请日：2006-03-20
申请人： Scott McLeod
发明人： Scott McLeod
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
摘要翻译：配置在半导体器件上的开关电容器电路中的电容器可以包括非常精确匹配的高电容密度的金属 - 金属电容器，使用顶板到底板的条纹电容来获得所需的电容值。可以将多晶硅板插入底部金属层下面作为屏蔽，并且自举到每个电容器的顶板，以便最小化和/或消除寄生的顶板对衬底电容。这可以释放用于形成额外的边缘电容的底部金属层，从而增加电容密度。通过仅根据从顶板到底板的边缘电容形成每个电容，不使用平行板电容，这可以减少电容器失配。也可以消除与衬底的寄生底板电容，仅剩余少量的自举多晶硅板的电容。电容器可以通过将每个电容器的顶板耦合到开关电容器电路中包括的放大器的差分输入中的相应一个来自举。

3. 发明授权

US08058929B1 Maintaining loop linearity in presence of threshold adjustment 有权
标题翻译：在存在阈值调整的情况下维持循环线性度
公开(公告)号：US08058929B1
公开(公告)日：2011-11-15
申请号：US12777027
申请日：2010-05-10
申请人： Scott McLeod
发明人： Scott McLeod
IPC分类号： H03F3/45
CPC分类号： H03F3/45973
摘要： In one embodiment, a method includes receiving, at a filter comprising a Miller amplifier, a differential data signal output by a limiting amplifier (LA), the data signal comprising an output direct current (DC) offset resulting at least in part from a threshold-adjustment signal applied to the LA or an intrinsic DC offset caused by physical characteristics of the LA. In one embodiment, the method additionally includes generating a compensation signal based on the threshold-adjustment signal, a polarity of the compensation signal being opposite a polarity of the threshold-adjustment signal or the DC offset, a magnitude of the compensation signal being a function of the magnitude of the threshold-adjustment signal. In one embodiment, the method further includes introducing the compensation signal to an internal node of the Miller amplifier to compensate for the DC offset to keep one or more amplifier stages of the Miller amplifier in their linear operating regions.
摘要翻译：在一个实施例中，一种方法包括在包括米勒放大器的滤波器处接收由限幅放大器（LA）输出的差分数据信号，所述数据信号包括至少部分地从阈值产生的输出直流（DC）偏移调整信号施加到LA或由LA的物理特性引起的固有DC偏移。在一个实施例中，该方法还包括基于阈值调整信号产生补偿信号，补偿信号的极性与阈值调整信号或DC偏移的极性相反，补偿信号的幅度是函数阈值调整信号的大小。在一个实施例中，该方法还包括将补偿信号引入到米勒放大器的内部节点以补偿DC偏移，以将米勒放大器的一个或多个放大器级保持在它们的线性工作区域中。

4. 发明申请

US20110273233A1 MAINTAINING LOOP LINEARITY IN PRESENCE OF THRESHOLD ADJUSTMENT 有权
标题翻译：维持阈值调整存在的环路线性
公开(公告)号：US20110273233A1
公开(公告)日：2011-11-10
申请号：US12777027
申请日：2010-05-10
申请人： Scott McLeod
发明人： Scott McLeod
IPC分类号： H03F3/45
CPC分类号： H03F3/45973
摘要： In one embodiment, a method includes receiving, at a filter comprising a Miller amplifier, a differential data signal output by a limiting amplifier (LA), the data signal comprising an output direct current (DC) offset resulting at least in part from a threshold-adjustment signal applied to the LA or an intrinsic DC offset caused by physical characteristics of the LA. In one embodiment, the method additionally includes generating a compensation signal based on the threshold-adjustment signal, a polarity of the compensation signal being opposite a polarity of the threshold-adjustment signal or the DC offset, a magnitude of the compensation signal being a function of the magnitude of the threshold-adjustment signal. In one embodiment, the method further includes introducing the compensation signal to an internal node of the Miller amplifier to compensate for the DC offset to keep one or more amplifier stages of the Miller amplifier in their linear operating regions.
摘要翻译：在一个实施例中，一种方法包括在包括米勒放大器的滤波器处接收由限幅放大器（LA）输出的差分数据信号，所述数据信号包括至少部分地从阈值产生的输出直流（DC）偏移调整信号施加到LA或由LA的物理特性引起的固有DC偏移。在一个实施例中，该方法还包括基于阈值调整信号产生补偿信号，补偿信号的极性与阈值调整信号或DC偏移的极性相反，补偿信号的幅度是函数阈值调整信号的大小。在一个实施例中，该方法还包括将补偿信号引入到米勒放大器的内部节点以补偿DC偏移，以将米勒放大器的一个或多个放大器级保持在它们的线性工作区域中。

5. 发明申请

US20070024332A1 All MOS power-on-reset circuit 审中-公开
标题翻译：所有MOS上电复位电路
公开(公告)号：US20070024332A1
公开(公告)日：2007-02-01
申请号：US11192152
申请日：2005-07-28
申请人： Scott McLeod
发明人： Scott McLeod
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A reliable, integrated POR (power-on-reset) circuit with a compact and small area. In one set of embodiments, the POR circuit comprises NMOS and PMOS devices, where a combination of the respective threshold voltages of the NMOS and PMOS devices is used to set the POR threshold. The NMOS and PMOS devices may be coupled in a configuration resulting in a POR threshold that is a function of the PMOS threshold voltage and a scaled version of the NMOS threshold voltage. The scaling factor may be a function of the transconductance parameters of the NMOS and PMOS devices. Additional NMOS devices may be configured in the POR circuit to provide hysteresis functionality, with one of the NMOS devices coupling to one of the original NMOS devices. The scaling factor used in determining the POR threshold in case of a falling supply voltage may then be a function of the transconductance parameters of the original NMOS and PMOS devices and the additional NMOS device coupling to one of the original NMOS devices.
摘要翻译：可靠的集成POR（上电复位）电路，结构紧凑，占地面积小。在一组实施例中，POR电路包括NMOS和PMOS器件，其中使用NMOS和PMOS器件的相应阈值电压的组合来设置POR阈值。 NMOS和PMOS器件可以以配置耦合，导致作为PMOS阈值电压和NMOS阈值电压的缩放版本的函数的POR阈值。缩放因子可以是NMOS和PMOS器件的跨导参数的函数。可以在POR电路中配置附加的NMOS器件以提供滞后功能，其中NMOS器件之一耦合到原始NMOS器件之一。在下降的电源电压的情况下用于确定POR阈值的缩放因子然后可以是原始NMOS和PMOS器件的跨导参数和耦合到原始NMOS器件之一的附加NMOS器件的函数。

6. 发明授权

US08659973B2 Sequential-write, random-read memory 有权
标题翻译：顺序写入，随机读取存储器
公开(公告)号：US08659973B2
公开(公告)日：2014-02-25
申请号：US12819082
申请日：2010-06-18
申请人： Scott McLeod , William W. Walker
发明人： Scott McLeod , William W. Walker
IPC分类号： G11C8/00 , G11C8/04 , G11C7/22
CPC分类号： G11C8/04 , G06F5/06 , G06F5/14 , G11C7/222 , G11C8/16 , G11C8/18
摘要： In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.
摘要翻译：在一个实施例中，一种方法包括响应于在包括多个字的存储器阵列处的写使能信号的断言，顺序地并且在第一时钟频率下将数据从存储器阵列的开始处开始写入存储器阵列直到内存数组已满。该方法包括，与基于在存储器阵列处接收到的读取地址的数据相比，以与从存储器阵列读取数据的第一时钟频率相比慢的第二时钟频率异步地和以第二时钟频率写入数据。

7. 发明授权

US08228105B2 Clock signal correction 有权
标题翻译：时钟信号校正
公开(公告)号：US08228105B2
公开(公告)日：2012-07-24
申请号：US12841097
申请日：2010-07-21
申请人： Scott McLeod , Nikola Nedovic
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H03K7/08
CPC分类号： H03K5/1565 , H03K2005/00052
摘要： In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.
摘要翻译：在一个实施例中，一种方法包括产生两个或多个时钟信号，顺序地选择每个时钟信号，以及调整所选择的一个时钟信号的相应时钟占空比，直到它基本上匹配预定的时钟占空比。各个时钟占空比的调整包括基于相应的时钟占空比生成控制信号，基于控制信号产生占空比失真（DCD）校正信号，调整所选择的一个的相应时钟占空比基于DCD校正信号的时钟信号，以及调整控制和DCD校正信号，并重新调整所选择的一个时钟信号的相应时钟占空比，直到所选择的一个时钟信号的相应时钟占空比基本上匹配预定的时钟占空比。

8. 发明申请

US20120019299A1 Clock Signal Correction 有权
标题翻译：时钟信号校正
公开(公告)号：US20120019299A1
公开(公告)日：2012-01-26
申请号：US12841097
申请日：2010-07-21
申请人： Scott McLeod , Nikola Nedovic
发明人： Scott McLeod , Nikola Nedovic
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00052
摘要： In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.
摘要翻译：在一个实施例中，一种方法包括产生两个或多个时钟信号，顺序地选择每个时钟信号，以及调整所选择的一个时钟信号的相应时钟占空比，直到它基本上匹配预定的时钟占空比。各个时钟占空比的调整包括基于相应的时钟占空比生成控制信号，基于控制信号产生占空比失真（DCD）校正信号，调整所选择的一个的相应时钟占空比基于DCD校正信号的时钟信号，以及调整控制和DCD校正信号，并重新调整所选择的一个时钟信号的相应时钟占空比，直到所选择的一个时钟信号的相应时钟占空比基本上匹配预定的时钟占空比。

9. 发明申请

US20070115042A1 Accurate temperature measurement method for low beta transistors 有权
标题翻译：低β晶体管的精确温度测量方法
公开(公告)号：US20070115042A1
公开(公告)日：2007-05-24
申请号：US11286706
申请日：2005-11-23
申请人： Scott McLeod , Aniruddha Bashar
发明人： Scott McLeod , Aniruddha Bashar
IPC分类号： H01L35/00
CPC分类号： G01K7/01
摘要： An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (ΔVBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.
摘要翻译：一种精确的温度监测系统，其使用精密电流控制电路将精确比例的电流施加到用于感测温度的半导体器件（可以是双极结型晶体管（BJT））。可以捕获与BJT的温度成比例的基极 - 发射极电压（DeltaV BAT）的变化，并将其提供给ADC，该ADC可产生对应于该温度的数值。精密电流控制电路可以被配置为产生参考电流，捕获BJT的基极电流，产生等于基极电流的总和和参考电流的倍数的组合电流，并将组合电流提供给发射器。响应于该组合电流，BJT的集电极电流将等于参考电流的倍数。因此，可以精确地控制由BJT传导的各种集电极电流的比率，从而导致更准确的温度测量。

10. 发明申请

US20060039445A1 Integrated resistance cancellation in temperature measurement systems 有权
公开(公告)号：US20060039445A1
公开(公告)日：2006-02-23
申请号：US10924176
申请日：2004-08-23
申请人： Scott McLeod
发明人： Scott McLeod
IPC分类号： G01K7/00
CPC分类号： G01K7/00 , G01K7/01
摘要： A temperature measurement device may be implemented by coupling a PN-junction, which may be comprised in a diode, to an analog-to-digital converter (ADC) that comprises an integrator. Different currents may be successively applied to the diode, resulting in different VBE values across the diode. The ΔVBE values thus obtained may be successively integrated. Appropriate values for the different currents may be determined based on a set of mathematical equations, each equation relating the VBE value to the temperature of the diode, the current applied to the diode and parasitic series resistance associated with the diode. When the current sources with the appropriate values are sequentially applied to the diode and the resulting diode voltage differences are integrated by the integrator comprised in the ADC, the error in the temperature measurement caused by series resistance is canceled in the ADC, and an accurate temperature reading of the diode is obtained from the output of the ADC.

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