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1. 发明授权

US07276435B1 Die level metal density gradient for improved flip chip package reliability 有权
标题翻译：芯片级金属密度梯度，提高了倒装芯片的封装可靠性
公开(公告)号：US07276435B1
公开(公告)日：2007-10-02
申请号：US11445657
申请日：2006-06-02
申请人： Scott K. Pozder , Kevin J. Hess , Ruiqi Tian , Edward O. Travis , Trent S. Uehling , Brett P. Wilkerson , Katie C. Yu
发明人： Scott K. Pozder , Kevin J. Hess , Ruiqi Tian , Edward O. Travis , Trent S. Uehling , Brett P. Wilkerson , Katie C. Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/13 , H01L24/14 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/13006 , H01L2224/13022 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13171 , H01L2224/13181 , H01L2224/13184 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.
摘要翻译：集成电路在顶表面上具有金属凸块，当形成金属凸块时，在底层上产生潜在的破坏性应力。确保底层金属互连层中的最小金属浓度得以实现，以减少破坏作用。最低金属浓度在角落最高，接下来沿着边界不在拐角处，接下来是内部。通常在金属凸块下方的互连层中的区域需要比不在凸块下方的相邻区域更多的浓度。对于远离集成电路表面的金属互连层，需要较小的浓度。所需的金属浓度通过首先尝试相对简单的解决方案实现。如果没有效果，则尝试不同的方法，直到达到最小浓度，或直到最后一次尝试。

2. 发明授权

US07247552B2 Integrated circuit having structural support for a flip-chip interconnect pad and method therefor 有权
标题翻译：具有用于倒装芯片互连焊盘的结构支撑的集成电路及其方法
公开(公告)号：US07247552B2
公开(公告)日：2007-07-24
申请号：US11033009
申请日：2005-01-11
申请人： Scott K. Pozder , Kevin J. Hess , Pak K. Leung , Edward O. Travis , Brett P. Wilkerson , David G. Wontor , Jie-Hua Zhao
发明人： Scott K. Pozder , Kevin J. Hess , Pak K. Leung , Edward O. Travis , Brett P. Wilkerson , David G. Wontor , Jie-Hua Zhao
IPC分类号： H01L21/4763
CPC分类号： H01L24/10 , H01L23/522 , H01L24/02 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.
摘要翻译：减轻施加到接合焊盘（32）的应力引起的缺陷的问题的技术包括：在实际制造集成电路（10）之前，将互连层（18,22,26）中的虚设金属线（74,76）以增加互连层的金属密度。当互连层之间的层间电介质（16,20,24）为低k材料时，这些问题更有可能。在每个接合垫周围和之下的临界区域或力区域（64）限定了由于与该接合焊盘的接触而可能发生缺陷的区域。金属密度低于某一百分比的这样关键区域中的任何互连层可能是互连层中缺陷的原因。在临界区域中具有低于该百分比的金属密度的任何互连层都添加有虚拟金属线。

3. 发明申请

US20110269300A1 Integrated Assist Features for Epitaxial Growth 有权
标题翻译：外延生长的综合辅助特征
公开(公告)号：US20110269300A1
公开(公告)日：2011-11-03
申请号：US13182568
申请日：2011-07-14
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/20 , G06F17/50
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

4. 发明授权

US08003539B2 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US08003539B2
公开(公告)日：2011-08-23
申请号：US11650253
申请日：2007-01-04
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/311
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

5. 发明授权

US07470624B2 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation 有权
标题翻译：用于补偿的外延生长体/ SOI混合瓦的综合辅助功能
公开(公告)号：US07470624B2
公开(公告)日：2008-12-30
申请号：US11651253
申请日：2007-01-08
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823481 , H01L21/823878 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307）在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

6. 发明申请

US20080168417A1 Integrated assist features for epitaxial growth bulk tiles with compensation 有权
标题翻译：具有补偿的外延生长块体的综合辅助功能
公开(公告)号：US20080168417A1
公开(公告)日：2008-07-10
申请号：US11650254
申请日：2007-01-04
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L29/045 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/31053 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据组导出第一沟槽CMP掩模集（307）和第一外延生长掩模组（309），其中通过去除子集（305）从第一数据集导出第一外延生长掩模集合，由所述第一数据集定义并且将所述瓦片的子集合合到所述第一外延生长掩模集合中的所述瓦片; 以及（c）重新配置第一沟槽CMP掩模集合以考虑第一外延生长掩模集合，从而限定第二沟槽CMP掩模集合（308）。

7. 发明授权

US06593226B2 Method for adding features to a design layout and process for designing a mask 有权
公开(公告)号：US06593226B2
公开(公告)日：2003-07-15
申请号：US09906874
申请日：2001-07-17
申请人： Edward O. Travis , Aykut Dengi , Sejal Chheda , Tat-Kwan Yu , Mark S. Roberton , Ruiqi Tian , Robert E. Boone , Alfred J. Reich
发明人： Edward O. Travis , Aykut Dengi , Sejal Chheda , Tat-Kwan Yu , Mark S. Roberton , Ruiqi Tian , Robert E. Boone , Alfred J. Reich
IPC分类号： H01L214763
CPC分类号： H01L21/31053 , H01L21/3212 , Y10S438/926
摘要： Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

8. 发明申请

US20080168418A1 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation 有权
标题翻译：用于补偿的外延生长体/ SOI混合瓦的综合辅助功能
公开(公告)号：US20080168418A1
公开(公告)日：2008-07-10
申请号：US11651253
申请日：2007-01-08
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L21/84 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823481 , H01L21/823878 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307）在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

9. 发明申请

US20080164559A1 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US20080164559A1
公开(公告)日：2008-07-10
申请号：US11650253
申请日：2007-01-04
申请人： Omar Zia , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/763 , H01L29/02
CPC分类号： H01L21/02595 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

10. 发明授权

US06459156B1 Semiconductor device, a process for a semiconductor device, and a process for making a masking database 有权
标题翻译：半导体装置，半导体装置的制造方法以及掩模数据库的制造方法
公开(公告)号：US06459156B1
公开(公告)日：2002-10-01
申请号：US09470873
申请日：1999-12-22
申请人： Edward O. Travis , Sejal N. Chheda , Bradley P. Smith , Ruiqi Tian
发明人： Edward O. Travis , Sejal N. Chheda , Bradley P. Smith , Ruiqi Tian
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L21/76802 , H01L22/20 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： At least one process-assist feature (210, 70, 706, 806, 506, 406, 608, 904, 1106, 108, 1206, 1208) at or near a via location of a wiring structure (75, 700, 800, 500, 400, 614, 908, 1205) within a semiconductor device is used to improve processing or processing margin during subsequent processing. For at least some of the embodiments of the present invention, the process-assist features feature (210, 70, 706, 806, 506, 406, 608, 904, 1106, 1108, 1206, 1208) help to make a flowable layer more uniform over via locations (84, 74, 704, 804, 504, 404, 603, 904, 1104, 1204). Typically, this can help in the formation of via openings. When a resist layer (204) is formed over the process-assist features, the resist layer (204) will have a more uniform thickness over most via locations within the device. When an insulating layer (197) is formed over the via locations, the insulating layer (107) will have a more uniform thickness over most via locations within the device. More control during resist exposure or via opening etching allow more process margin. The embodiments described herein illustrate the flexibility in placing process-assist features.
摘要翻译：在布线结构（75,700,800,500,500）的通孔位置处或附近的至少一个过程辅助特征（210,70,706,806,106,406,608,904,1106,108,120,140,1106,106,108,120,1406），400,614,908,1205）用于在后续处理期间改善处理或处理余量。对于本发明的至少一些实施例，过程辅助特征特征（210,70,706,806,506,406,608,904,1106,180,1206,1208）有助于使可流动层更多通过位置（84,74,704,804,504,404,603,904,1104,1204）均匀化。通常，这有助于形成通孔。当在工艺辅助特征上形成抗蚀剂层（204）时，抗蚀剂层（204）在装置内的大多数通孔位置上将具有更均匀的厚度。当绝缘层（197）形成在通孔位置上方时，绝缘层（107）在装置内的大多数通孔位置上将具有更均匀的厚度。抗蚀剂曝光或通过开口蚀刻的更多控制允许更多的工艺余量。这里描述的实施例说明了放置过程辅助特征的灵活性。

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