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1. 发明授权

US5590297A Address generation unit with segmented addresses in a mircroprocessor 失效
标题翻译：在微处理器中具有分段地址的地址生成单元
公开(公告)号：US5590297A
公开(公告)日：1996-12-31
申请号：US176066
申请日：1994-01-04
申请人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
发明人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
IPC分类号： G06F9/34 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/0292
摘要： A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.
摘要翻译：一种微处理器，包括用于执行算术功能的执行单元，用于确定要访问的条目的提取单元，用于从存储器中的存储访问该条目的发布单元，以及用于生成该条目的地址的地址生成单元。用于生成地址的基本部分和限制值存储在单独的段中。这些分离的部分被重新排列，以形成具有连续的基极和极限位的段。然后将连续的基数和极限值存储在寄存器文件中。基数和限制副本存储在控制寄存器中并广播到其他单元。此外，可复位的无效位存储在另一个寄存器中。此外，AGU包括用于选择寄存器文件的特定字段并对所选择的文件执行读/写操作的装置。

2. 发明授权

US5517657A Segment register file read and write pipeline 失效
标题翻译：段寄存器文件读写管道
公开(公告)号：US5517657A
公开(公告)日：1996-05-14
申请号：US220693
申请日：1994-03-30
申请人： Scott D. Rodgers , Kamla P. Huck
发明人： Scott D. Rodgers , Kamla P. Huck
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3885 , G06F9/30101 , G06F9/3824 , G06F9/3867 , G06F9/3875
摘要： A mechanism and procedure for providing an efficient pipeline for reading and writing information to a multiple ported segment register file (SRF) in different pipestages. The present invention is operable, in one embodiment, within an address generation unit (AGU) of a processor and is implemented to write the SRF during a particular clock phase of a pipestage and to read to the SRF during another clock phase of another pipestage of the AGU pipeline of a pipelined processor. The read and write of different pipestages associated with separate instructions may occur within a same clock cycle. The write occurs before the read. By reading and writing to the AGU in alternate clock phases, the read and write operations of the SRF do not conflict even though they span different pipestages of the pipeline. Therefore, pipestages of the present invention are not in resource conflict over the SRF read and write operations which occur in a same clock cycle. Specifically, within the scope of the present invention, the SRF may be read during the low phase of a clock cycle while the SRF may be written during the high phase of a clock cycle for different instructions. Alternatively, the above phase relationships may be inverted.
摘要翻译：一种用于在不同管道中为多端口段寄存器文件（SRF）读取和写入信息的有效管道的机制和过程。本发明在一个实施例中可在处理器的地址生成单元（AGU）内操作，并且被实现为在分支的特定时钟相位期间写入SRF，并且在另一个分支的另一个时间段期间读取到SRF 流水线处理器的AGU管道。与单独指令相关联的不同管道的读取和写入可以在相同的时钟周期内进行。写入发生在读取之前。通过在备用时钟阶段读取和写入AGU，SRF的读取和写入操作即使跨越管道的不同管道也不会发生冲突。因此，在相同的时钟周期中发生的SRF读和写操作，本发明的分支管理不是资源冲突的。具体地说，在本发明的范围内，可以在时钟周期的低相位期间读取SRF，同时可以在针对不同指令的时钟周期的高相位期间写入SRF。或者，上述相位关系可以反转。

3. 发明授权

US5749084A Address generation unit with segmented addresses in a microprocessor 失效
标题翻译：在微处理器中具有分段地址的地址生成单元
公开(公告)号：US5749084A
公开(公告)日：1998-05-05
申请号：US634092
申请日：1996-04-17
申请人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
发明人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
IPC分类号： G06F9/34 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/06
CPC分类号： G06F12/1036 , G06F12/0292
摘要： A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
摘要翻译：一种具有地址生成单元（AGU）的处理器，用于生成与要获取的条目相对应的地址。 AGU包括用于存储地址段的段寄存器文件和用于重新排列第一地址段的不连续基地址和限制位位置的电路，以便生成具有连续顺序的所有基址和限制位的第二地址段。 AGU还包括用于执行单个微指令以对存储在段寄存器堆中的第二地址段的选定字段执行读和写操作的电路。

4. 发明申请

US20140281376A1 Creating An Isolated Execution Environment In A Co-Designed Processor 有权
标题翻译：在协同设计的处理器中创建一个隔离的执行环境
公开(公告)号：US20140281376A1
公开(公告)日：2014-09-18
申请号：US13795720
申请日：2013-03-12
申请人： Koichi Yamada , Palanivel Rajan Shanmugavelayutham , Scott D. Rodgers , Barry E. Huntley , James D. Beaney, JR. , Boaz Tamir
发明人： Koichi Yamada , Palanivel Rajan Shanmugavelayutham , Scott D. Rodgers , Barry E. Huntley , James D. Beaney, JR. , Boaz Tamir
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/44 , G06F9/45516 , G06F9/45533 , Y02D10/26 , Y02D10/28
摘要： In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有生成第一代码段的二进制转换和将二进制转换存储在转换高速缓存中的代码的二进制转换（BT）容器，用于管理BT容器的主机实体逻辑，并且识别第一代码段和用于将BT容器与软件堆栈隔离的保护逻辑。这样，BT容器被配置为对软件堆栈是透明的。描述和要求保护其他实施例。

5. 发明申请

US20140006739A1 Systems, Apparatuses, and Methods for Implementing Temporary Escalated Privilege 审中-公开
标题翻译：实施临时升级特权的系统，设备和方法
公开(公告)号：US20140006739A1
公开(公告)日：2014-01-02
申请号：US13539132
申请日：2012-06-29
申请人： Martin G. Dixon , Gilbert Neiger , Robert S. Chappell , Scott D. Rodgers , Barry E. Huntley
发明人： Martin G. Dixon , Gilbert Neiger , Robert S. Chappell , Scott D. Rodgers , Barry E. Huntley
IPC分类号： G06F12/14
CPC分类号： G06F12/14 , G06F12/1491
摘要： Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.
摘要翻译：用于临时允许从较高特权级别访问较低权限级别的系统，装置和方法的实施例。

6. 发明授权

US08521969B2 Apparatus and method for directing micro architectural memory region accesses 有权
标题翻译：用于指导微架构存储器区域访问的装置和方法
公开(公告)号：US08521969B2
公开(公告)日：2013-08-27
申请号：US11546710
申请日：2006-10-11
申请人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
发明人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/1441 , G06F2221/2141
摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
摘要翻译：在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

7. 发明授权

US08402252B2 Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode 有权
标题翻译：用三字节转义操作码来排除指令特定操作码的地址格式字段的指令长度
公开(公告)号：US08402252B2
公开(公告)日：2013-03-19
申请号：US13417241
申请日：2012-03-10
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

8. 发明申请

US20150007304A1 METHOD AND APPARATUS FOR SECURING A DYNAMIC BINARY TRANSLATION SYSTEM 有权
标题翻译：用于保护动态二进制翻译系统的方法和装置
公开(公告)号：US20150007304A1
公开(公告)日：2015-01-01
申请号：US13930766
申请日：2013-06-28
申请人： Lior Malka , Koichi Yamada , Palanivelrajan Shanmugavelayutham , Barry E. Huntley , Scott D. Rodgers , James D. Beaney, JR.
发明人： Lior Malka , Koichi Yamada , Palanivelrajan Shanmugavelayutham , Barry E. Huntley , Scott D. Rodgers , James D. Beaney, JR.
IPC分类号： G06F21/52
CPC分类号： G06F21/74 , G06F21/54
摘要： A processor and method are described for managing different privilege levels associated with different types of program code, including binary translation program code. For example, one embodiment of a method comprises entering into one of a plurality of privilege modes responsive to detecting the execution of a corresponding one of a plurality of different types of program code including native executable program code, translated executable program code, and binary translation program code. In one embodiment, the binary translation program code includes sub-components each of which are associated with a different privilege level for improved security.
摘要翻译：描述了处理器和方法，用于管理与不同类型的程序代码相关联的不同特权级别，包括二进制翻译程序代码。例如，方法的一个实施例包括响应于检测到多个不同类型的程序代码中的相应的一个程序代码的执行，包括本机可执行程序代码，翻译的可执行程序代码和二进制转换，来进入多个特权模式之一程序代码。在一个实施例中，二进制翻译程序代码包括子组件，每个子组件与不同的权限级别相关联，以提高安全性。

9. 发明申请

US20120173852A1 INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
标题翻译：使用3字节ESCAPE操作码的指令集扩展
公开(公告)号：US20120173852A1
公开(公告)日：2012-07-05
申请号：US13417241
申请日：2012-03-10
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

10. 发明授权

US07966476B2 Determining length of instruction with escape and addressing form bytes without evaluating opcode 有权
标题翻译：使用转义和寻址格式字节确定指令的长度，而不评估操作码
公开(公告)号：US07966476B2
公开(公告)日：2011-06-21
申请号：US12039719
申请日：2008-02-28
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

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