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1. 发明授权

US07560387B2 Opening hard mask and SOI substrate in single process chamber 失效
标题翻译：在单处理室中打开硬掩模和SOI衬底
公开(公告)号：US07560387B2
公开(公告)日：2009-07-14
申请号：US11275707
申请日：2006-01-25
申请人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
发明人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/31116
摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.
摘要翻译：公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅衬垫层，二氧化硅（SiO 2）衬垫层和叠层 SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

2. 发明申请

US20080064178A1 DEEP TRENCH CAPACITOR THROUGH SOI SUBSTRATE AND METHODS OF FORMING 有权
标题翻译：通过SOI衬底的深度电容器和形成方法
公开(公告)号：US20080064178A1
公开(公告)日：2008-03-13
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

3. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

4. 发明申请

US20110092043A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20110092043A1
公开(公告)日：2011-04-21
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

5. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

6. 发明授权

US07888723B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US07888723B2
公开(公告)日：2011-02-15
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

7. 发明授权

US07575970B2 Deep trench capacitor through SOI substrate and methods of forming 有权
标题翻译：深沟槽电容器通过SOI衬底和成型方法
公开(公告)号：US07575970B2
公开(公告)日：2009-08-18
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

8. 发明申请

US20130328174A1 Edge Protection of Bonded Wafers During Wafer Thinning 有权
标题翻译：晶圆薄化期间粘合晶片的边缘保护
公开(公告)号：US20130328174A1
公开(公告)日：2013-12-12
申请号：US13489861
申请日：2012-06-06
申请人： Douglas C. La Tulipe, JR. , Spyridon Skordas , Tuan A. Vo , Kevin R. Winstel
发明人： Douglas C. La Tulipe, JR. , Spyridon Skordas , Tuan A. Vo , Kevin R. Winstel
IPC分类号： H01L23/58 , H01L21/30
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译：边缘保护键合半导体晶片的方法。第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。第一，第二和第三半导体晶片形成晶片叠层。晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。

9. 发明申请

US20120175789A1 ALIGNMENT MARKS TO ENABLE 3D INTEGRATION 有权
标题翻译：对齐标记可以实现3D集成
公开(公告)号：US20120175789A1
公开(公告)日：2012-07-12
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Patrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Patrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译：公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

10. 发明授权

US09214435B2 Via structure for three-dimensional circuit integration 有权
标题翻译： Via结构用于三维电路集成
公开(公告)号：US09214435B2
公开(公告)日：2015-12-15
申请号：US13476056
申请日：2012-05-21
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L25/065 , H01L23/538 , H01L27/06
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/5386 , H01L24/80 , H01L24/82 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/0688 , H01L2224/02205 , H01L2224/08145 , H01L2224/0905 , H01L2224/80896 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/0002 , H01L2924/14 , H01L2924/3701 , H01L2924/00 , H01L2224/80
摘要： Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
摘要翻译：公开了结合三维积分的电路及其制造方法。一个电路包括底层和多个上层。底层包括连接到底层中的功能部件的底部着陆垫。此外，上层堆叠在底层上方。每个上层包括相应的上层板，其连接到各个上层中的各个功能部件。着陆焊盘通过单个导电通孔耦合，并且在底层和上层的堆叠中对准，使得每个着陆焊盘从堆叠中的相邻层中的任何一个着陆焊盘偏移至少一个预定金额。

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