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    • 1. 发明授权
      US09070482B2 Multi-chip package semiconductor memory device 有权
    • Multi-chip package semiconductor memory device
    • 多芯片封装半导体存储器件
    • US09070482B2
    • 2015-06-30
    • US13159517
    • 2011-06-14
    • Satoshi Miyazaki , Hidekazu Nasu
    • Satoshi Miyazaki , Hidekazu Nasu
    • G06F12/00 , G06F13/00 , G06F13/28 , G11C29/00
    • G11C29/70 , G11C29/76 , H01L2224/48147
    • An MCP type semiconductor memory device having a defective cell remedy function, enables easy design and manufacture while minimizing chip area increase. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information.
    • 具有缺陷电池补救功能的MCP型半导体存储器件能够容易地进行设计和制造，同时最小化芯片面积增加。 半导体存储器件包括存储器芯片和存储器控制器芯片，其根据从外部接收的访问请求来指定存储器芯片的地址，并控制对指定地址的访问。 每个存储器芯片包括第一和第二存储区域以及信息保持器，其保存表示第一和第二存储区域中的地址之间的关联的地址信息。 存储器控制器芯片包括：地址转换部，其在接收到由地址信息指示的第一存储区域中访问特定地址的请求时，通过将第一存储区域中的特定地址转换为第二存储区域中的地址来执行地址指定 存储区域基于由地址信息表示的关联而与特定地址相对应。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US08723303B2 Multi-chip package semiconductor memory device 有权
    • Multi-chip package semiconductor memory device
    • 多芯片封装半导体存储器件
    • US08723303B2
    • 2014-05-13
    • US13159513
    • 2011-06-14
    • Hidekazu Nasu , Satoshi Miyazaki
    • Hidekazu Nasu , Satoshi Miyazaki
    • H01L23/02 , H01L23/48
    • G11C5/02 , H01L25/0652 , H01L2224/48145 , H01L2224/48147 , H01L2224/49171 , H01L2224/49175 , H01L2225/06562 , H01L2924/09701 , H01L2924/181 , H01L2924/00 , H01L2924/00012
    • An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip adjacent the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.
    • 一种MCP型半导体存储器件，其结构是将包括多个堆叠的存储器芯片的堆叠存储器芯片和存储器控制器芯片并置在基板上，这实现了封装尺寸的减小。 半导体存储器件包括堆叠存储器芯片，其包括多个层叠的存储器芯片，其上提供有堆叠存储器芯片的衬底以及与衬底上的堆叠存储器芯片相邻的存储器控​​制器芯片。 堆叠存储器芯片被构造成使得上部存储器芯片被堆叠以便相对于位于上部存储器芯片正下方的存储器芯片朝向存储器控制器芯片的安装位置移动。 存储器控制器芯片的至少一部分被接收在衬底和向存储器控制器芯片突出的堆叠存储器芯片的一部分之间的空间内。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明申请
      US20110314234A1 MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE 有权
    • MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE
    • 多芯片封装半导体存储器件
    • US20110314234A1
    • 2011-12-22
    • US13159517
    • 2011-06-14
    • Satoshi Miyazaki , Hidekazu Nasu
    • Satoshi Miyazaki , Hidekazu Nasu
    • G06F12/00
    • G11C29/70 , G11C29/76 , H01L2224/48147
    • An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information.
    • 提供具有缺陷电池补救功能的MCP型半导体存储器件，其能够在最小化芯片面积增加的同时实现容易的设计和制造。 半导体存储器件包括存储器芯片和存储器控制器芯片，其根据从外部接收的访问请求来指定存储器芯片的地址，并控制对指定地址的访问。 每个存储器芯片包括第一和第二存储区域以及信息保持器，其保存表示第一和第二存储区域中的地址之间的关联的地址信息。 存储器控制器芯片包括：地址转换部，其在接收到由地址信息指示的第一存储区域中访问特定地址的请求时，通过将第一存储区域中的特定地址转换为第二存储区域中的地址来执行地址指定 存储区域基于由地址信息表示的关联而与特定地址相对应。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20110309525A1 MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE 有权
    • MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE
    • 多芯片封装半导体存储器件
    • US20110309525A1
    • 2011-12-22
    • US13159513
    • 2011-06-14
    • Hidekazu Nasu , Satoshi Miyazaki
    • Hidekazu Nasu , Satoshi Miyazaki
    • H01L23/538
    • G11C5/02 , H01L25/0652 , H01L2224/48145 , H01L2224/48147 , H01L2224/49171 , H01L2224/49175 , H01L2225/06562 , H01L2924/09701 , H01L2924/181 , H01L2924/00 , H01L2924/00012
    • An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.
    • 提供一种MCP型半导体存储器件，其具有将包括多个堆叠的存储器芯片的堆叠存储器芯片和存储器控制器芯片并置在基板上的结构，这实现了封装尺寸的减小。 半导体存储器件包括堆叠存储器芯片，其包括多个层叠的存储器芯片，其上提供有堆叠存储器芯片的衬底以及与衬底上的堆叠存储器芯片相邻设置的存储器控​​制器芯片。 堆叠存储器芯片被构造成使得上部存储器芯片被堆叠以便相对于位于上部存储器芯片正下方的存储器芯片朝向存储器控制器芯片的安装位置移动。 存储器控制器芯片的至少一部分被接收在衬底和向存储器控制器芯片突出的堆叠存储器芯片的一部分之间的空间内。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US08363709B2 Transmission apparatus and line quality evaluating method 有权
    • Transmission apparatus and line quality evaluating method
    • 传输装置和线路质量评估方法
    • US08363709B2
    • 2013-01-29
    • US12625709
    • 2009-11-25
    • Satoshi Miyazaki , Takashi Kuwabara
    • Satoshi Miyazaki , Takashi Kuwabara
    • H04B17/00
    • H04J3/085 , H04J2203/0057 , H04J2203/0085 , H04J2203/0094 , H04L1/20
    • A transmission apparatus includes a test signal control unit that copies a test signal of a pseudo-random bit sequence and controls insertion of the same test signal in each member of a plurality of members of a concatenation signal, a concatenation signal transmitting unit that transmits each member of the concatenation signal with the test signal inserted therein by the test signal control unit to other apparatus via a plurality of transmission paths, a concatenation signal receiving unit that receives from the other apparatus each member of a plurality of members of a concatenation signal, and an individual-line-quality calculating unit that, using a test signal inserted in the members of the concatenation signal received by the concatenation signal receiving unit, individually evaluates each member of the concatenation signal received by the concatenation signal receiving unit and calculates a line quality of each transmission path.
    • 传输装置包括：测试信号控制单元，其复制伪随机比特序列的测试信号，并控制相同测试信号在级联信号的多个成员的每个成员中的插入;级联信号发送单元， 连接信号的成员，其中测试信号通过测试信号控制单元经由多个传输路径插入到其他设备中;级联信号接收单元，从其他设备接收串联信号的多个成员的每个成员， 以及单线质量计算单元，使用插入在级联信号接收单元接收的级联信号的成员中的测试信号，分别评估由级联信号接收单元接收的级联信号的每个成员，并计算一行 每个传输路径的质量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07978256B2 Imaging device having manual and auto focus and a control method for the imaging device 有权
    • Imaging device having manual and auto focus and a control method for the imaging device
    • 具有手动和自动对焦的成像装置和用于成像装置的控制方法
    • US07978256B2
    • 2011-07-12
    • US12193526
    • 2008-08-18
    • Keiji Kunishige , Satoshi Miyazaki
    • Keiji Kunishige , Satoshi Miyazaki
    • G03B13/20 , H04N5/232
    • H04N5/23293 , H04N5/23212
    • An imaging device, comprising a photographing lens having a manual focus mechanism, an imaging unit for receiving subject light flux, that has been made incident by the photographing lens, on an imaging surface, a display unit for carrying out a live view display operation using image data acquired by the imaging unit, a contrast AF unit for obtaining contrast information of the subject information from image data acquired by the imaging unit and guiding the photographing lens into a specified focus permissible range based on the contrast information, and a control unit for, when a manual focus operation is carried out after executing a focus adjustment operation using the contrast AF unit during the live view display, carrying out control so that there is a transition to a shooting operation without again executing the focus adjustment operation.
    • 一种成像装置，包括具有手动对焦机构的摄影镜头，用于接收被拍摄镜头入射的被摄体光束的成像单元在成像表面上的显示单元，用于执行使用 由成像单元获取的图像数据，对比度AF单元，用于从由所述成像单元获取的图像数据获得所述对象信息的对比度信息，并且基于所述对比度信息将所述拍摄透镜引导到指定的焦点允许范围;以及控制单元， 当在实时取景显示期间执行使用对比度AF单元的聚焦调整操作之后执行手动对焦操作时，进行控制，使得转到拍摄操作而不再次执行聚焦调整操作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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